Re: [PATCH] Fix incorrect flush address in direct page table reclaim

On Mon, Aug 3, 2026 at 6:30=E2=80=AFPM Andrew Morton <akpm@linux-foundation=
.org> wrote:
>
> On Mon,  3 Aug 2026 17:37:08 -0700 [email protected] wrote:
>
> > From: Andy Lutomirski <[email protected]>
> >
> > When zap_pte_range reclaims a page table, it does:
> >
> >     pte_free_tlb(tlb, pmd_pgtable(pmdval), addr);
> >
> > and this is unconditionally wrong: if this code executes, addr *always*
> > points one past the end of the range covered by the table.  The addr
> > parameter is used to flush the TLB (really the paging-structure-cache)
> > to drop references to the to-be-freed table, and any architecture that
> > cares about the parameter will flush the wrong address.  (But they'll
> > still free the correct page).
> >
> > I think it's worth contemplating why the kernel works at all.
> >
> > If we hit the offending line of code, we will first clear the PMD entry
> > (line 1954, zap_empty_pte_table), then we will issue pending flushes if
> > force_flush is set (tlb_flush_mmu_tlbonly(tlb)), then we will skip the
> > retry on line 1979 (phew!), and then we will do the offending
> > pte_free_tlb call.  *Or* we will clear the PMD entry immediately before
> > pte_free_tlb (line 1983, zap_pte_table_if_empty).
> >
> > If we have any pending flushes (i.e. we actually zapped any last-level
> > entries) at the time we clear the PMD entry, then the flush really ough=
t
> > to flush all references to the table (Linus certainly seems to think it
> > will on all architectures [0]).
> >
> > The condition under which we have no accumulated flushes at the time of
> > the clear is very complex (the whole zap_pte_range function has absurdl=
y
> > complex control flow).  If we do hit the bad case, then we will end up
> > clearing the PMD entry after the last time the range is flushed, and an=
y
> > CPU is free to cache a reference to the (empty) page table.  If this
> > happens due to an ordinary read or write, it would segfault, so it woul=
d
> > be rare.  But the cache could be speculatively filled as well.  Then
> > we'll flush the wrong address and then free and possibly reuse the
> > table.
> >
> > On x86, even flushing the wrong address works on non-KPTI Intel systems
> > because INVLPG flushes *all* paging-structure-caches, not just the ones
> > for the target address.  But INVPCID does not, and flush_tlb_one_user
> > will use INVPCID if it's available.  And then we're toast.  AMD systems
> > are more susceptible: we set the EFER.TCE bit, which makes even INVLPG
> > only flush the target address.
> >
> > P.S. IMO zap_pte_range is a mess.  The control flow is excessively
> > complex.  The direct_reclaim variable itself has a confused meaning --
> > for the first part of the function it means, approximately, "we should
> > free the table if can_reclaim_pt".  But, later on, it means "we ALREADY
> > reclaimed the table".  And the goto retry on line 1979 is IMO just
> > asking for trouble if the condition ever changes such that it might
> > happen after clearing the PMD.
> >
> > I think this might fix an issue in ripgrep reported here:
> > https://github.com/BurntSushi/ripgrep/issues/3494
>
> Huh, cool.  Very recently I was scratching my head at Daniel's ripgrep
> report.  Upon which he obviously did a ton of work (many thanks).
>
>         https://github.com/dfoxfranke/ripgrep-3494-analysis

I'm pretty sure that's AI-generated.

>
> Daniel also pointed a finger at 4c640eb4181c ("mm: move pte table
> reclaim code to memory.c").
>
> The manifestation is that a tiny race window causes the zero page to
> magically appear where an anon page was expected.

The analysis says:

pagemap reports the page present, soft-dirty, with PFN 0 =E2=80=94 the
kernel's zero page.

ahem.  I would be quite surprised if pfn 0 is the zero page.

If whatever code the AI wrote that generated its trace is actually
correct and there was a PTE entry with pfn 0 and the present bit set,
then maybe we have a genuine race that corrupts a page table.  But the
analysis seems quite sloppy and I'm disinclined to trust it too much.
(A quick experiment suggests that even GPT-5.6-Sol high (which is
supposedly pretty good) will rapidly go off the rails if you ask it a
leading-in-the-wrong-direction question about the kernel.)

In any case, the original reporter was using an AMD system, and the
bug seems extremely sensitive to tiny details, both of which are
consistent with the possibility of a narrow page table caching bug
like this.  I'm frankly a bit amazed that he and his AI were able to
reproduce it as many times as they apparently did.  I wonder if the
specific offending assembly caused the CPU to somewhat reliably
speculatively fill the paging structure cache during the narrow window
after the last correct flush and before the PMD entry was cleared --
if so, this would be consistent with the AI's observation that even
tiny changes to the asm seemed to make the bug go away.

--Andy