[RFC PATCH v3 10/19] target/arm: Add Nvidia Grace named model
Khushit Shah <[email protected]>
| Newsgroups | org.nongnu.qemu-arm,dev.linux.lists.kvmarm,org.nongnu.qemu-devel |
|---|---|
| Message-ID | <[email protected]> |
Add Nvidia Grace named model alongside its hierarchy (neoverse-v2, armv9-a) Field values were derived from the ID register view that KVM exposes to QEMU with -cpu host on an Nvidia Grace system. Signed-off-by: Khushit Shah <[email protected]> --- hw/arm/virt.c | 3 + target/arm/arm-cpu-models.c | 154 +++++++++++++++++++++++++++++++++++- 2 files changed, 156 insertions(+), 1 deletion(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 34e56dc1f1..3b27c7a710 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -3816,6 +3816,9 @@ static GPtrArray *virt_get_valid_cpu_types(const MachineState *ms) g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("arm-v8_4-a-v1"))); g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-v1-v1"))); g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("graviton3-v1"))); + g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("arm-v9_0-a-v1"))); + g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("neoverse-v2-v1"))); + g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("grace-v1"))); } g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("max"))); diff --git a/target/arm/arm-cpu-models.c b/target/arm/arm-cpu-models.c index 747e0df010..40e8578591 100644 --- a/target/arm/arm-cpu-models.c +++ b/target/arm/arm-cpu-models.c @@ -14,7 +14,9 @@ * arm-v8_4-a-v1 ARMv8.4-A architectural mandate * neoverse-v1-v1 Neoverse V1 (TRM 102649) * graviton3-v1 AWS Graviton3 - * + * arm-v9_0-a-v1 ARMv9.0-A architectural deltas + * neoverse-v2-v1 Neoverse V2 (TRM 102375) + * grace-v1 NVIDIA Grace * SPDX-License-Identifier: GPL-2.0-or-later */ @@ -197,6 +199,141 @@ static const ArmModelPropValue graviton3_v1_props[] = { MODEL_PROP_END, }; +static const ArmModelPropValue armv9_0_a_v1_props[] = { + MODEL_PROP("SYSREG_ID_AA64PFR1_EL1_BT", NUM, 1), + + MODEL_PROP("SYSREG_ID_AA64PFR0_EL1_CSV2", NUM, 1), + MODEL_PROP("SYSREG_ID_AA64PFR1_EL1_CSV2_frac", NUM, 0), + + MODEL_PROP("SYSREG_ID_AA64PFR0_EL1_CSV3", NUM, 1), + MODEL_PROP("SYSREG_ID_AA64ISAR1_EL1_DPB", NUM, 2), + MODEL_PROP("SYSREG_ID_AA64MMFR2_EL1_E0PD", NUM, 1), + MODEL_PROP("SYSREG_ID_AA64ISAR1_EL1_SB", NUM, 1), + MODEL_PROP("SYSREG_ID_AA64ISAR1_EL1_SPECRES", NUM, 1), + MODEL_PROP("SYSREG_ID_AA64PFR1_EL1_SSBS", NUM, 2), + + MODEL_PROP("SYSREG_ID_AA64DFR0_EL1_DoubleLock", NUM, 0xF), + MODEL_PROP("SYSREG_ID_AA64PFR0_EL1_FP", NUM, 0), + MODEL_PROP("SYSREG_ID_AA64PFR0_EL1_AdvSIMD", NUM, 0), + MODEL_PROP("SYSREG_ID_AA64ISAR0_EL1_TS", NUM, 2), + MODEL_PROP("SYSREG_ID_AA64ISAR1_EL1_FRINTTS", NUM, 1), + MODEL_PROP("SYSREG_ID_AA64ISAR0_EL1_RDM", NUM, 1), + MODEL_PROP("SYSREG_ID_AA64ISAR0_EL1_DP", NUM, 1), + MODEL_PROP("SYSREG_ID_AA64ISAR0_EL1_FHM", NUM, 1), + MODEL_PROP("SYSREG_ID_AA64ISAR1_EL1_FCMA", NUM, 1), + MODEL_PROP("SYSREG_ID_AA64ISAR1_EL1_JSCVT", NUM, 1), + + MODEL_PROP("SYSREG_ID_AA64PFR0_EL1_SVE", NUM, 1), + MODEL_PROP("SYSREG_ID_AA64PFR0_EL1_SEL2", NUM, 1), + MODEL_PROP("SYSREG_ID_AA64MMFR1_EL1_VH", NUM, 1), + MODEL_PROP("SYSREG_ID_AA64MMFR1_EL1_XNX", NUM, 1), + + MODEL_PROP_END, +}; + + +static const ArmModelPropValue neoverse_v2_v1_props[] = { + MODEL_PROP("SYSREG_MIDR_EL1_Implementer", NUM, 0x41), + MODEL_PROP("SYSREG_MIDR_EL1_Variant", NUM, 0x0), + MODEL_PROP("SYSREG_MIDR_EL1_Architecture", NUM, 0xF), + MODEL_PROP("SYSREG_MIDR_EL1_PartNum", NUM, 0xD4F), + MODEL_PROP("SYSREG_MIDR_EL1_Revision", NUM, 0x2), + + MODEL_PROP("SYSREG_ID_AA64DFR0_EL1_BRPs", NUM, 0x5), + MODEL_PROP("SYSREG_ID_AA64DFR0_EL1_WRPs", NUM, 0x3), + MODEL_PROP("SYSREG_ID_AA64DFR0_EL1_CTX_CMPs", NUM, 0x1), + MODEL_PROP("SYSREG_ID_AA64DFR0_EL1_PMUVer", NUM, 6), + + MODEL_PROP("SYSREG_ID_AA64ISAR0_EL1_TLB", NUM, 2), + + MODEL_PROP("SYSREG_ID_AA64ISAR1_EL1_BF16", NUM, 1), + MODEL_PROP("SYSREG_ID_AA64ISAR1_EL1_DGH", NUM, 1), + MODEL_PROP("SYSREG_ID_AA64ISAR1_EL1_I8MM", NUM, 1), + + MODEL_PROP("SYSREG_ID_AA64PFR0_EL1_FP", NUM, 1), + MODEL_PROP("SYSREG_ID_AA64PFR0_EL1_AdvSIMD", NUM, 1), + + MODEL_PROP("SYSREG_ID_AA64PFR0_EL1_RAS", NUM, 2), + MODEL_PROP("SYSREG_ID_AA64PFR1_EL1_RAS_frac", NUM, 0), + + /* + * V2 silicon may report CSV2=2 (FEAT_CSV2_2) per TRM page 392, but + * KVM clamps the guest-visible limit to 1. + */ + MODEL_PROP("SYSREG_ID_AA64PFR0_EL1_CSV2", NUM, 1), + MODEL_PROP("SYSREG_ID_AA64PFR1_EL1_CSV2_frac", NUM, 0), + + MODEL_PROP("SYSREG_ID_AA64MMFR0_EL1_PARange", NUM, 5), + MODEL_PROP("SYSREG_ID_AA64MMFR0_EL1_ASIDBits", NUM, 2), + MODEL_PROP("SYSREG_ID_AA64MMFR0_EL1_BigEnd", NUM, 1), + MODEL_PROP("SYSREG_ID_AA64MMFR0_EL1_SNSMem", NUM, 1), + MODEL_PROP("SYSREG_ID_AA64MMFR0_EL1_TGran16", NUM, 1), + MODEL_PROP("SYSREG_ID_AA64MMFR0_EL1_TGran64", NUM, 0), + MODEL_PROP("SYSREG_ID_AA64MMFR0_EL1_TGran4", NUM, 0), + MODEL_PROP("SYSREG_ID_AA64MMFR0_EL1_TGran16_2", NUM, 2), + MODEL_PROP("SYSREG_ID_AA64MMFR0_EL1_TGran64_2", NUM, 2), + MODEL_PROP("SYSREG_ID_AA64MMFR0_EL1_TGran4_2", NUM, 2), + + MODEL_PROP("SYSREG_ID_AA64MMFR1_EL1_HAFDBS", NUM, 2), + MODEL_PROP("SYSREG_ID_AA64MMFR1_EL1_VMIDBits", NUM, 2), + MODEL_PROP("SYSREG_ID_AA64MMFR1_EL1_HPDS", NUM, 2), + MODEL_PROP("SYSREG_ID_AA64MMFR1_EL1_PAN", NUM, 3), + MODEL_PROP("SYSREG_ID_AA64MMFR1_EL1_ECBHB", NUM, 0), + MODEL_PROP("SYSREG_ID_AA64MMFR1_EL1_SpecSEI", NUM, 0), + + MODEL_PROP("SYSREG_ID_AA64MMFR2_EL1_FWB", NUM, 1), + MODEL_PROP("SYSREG_ID_AA64MMFR2_EL1_ST", NUM, 1), + MODEL_PROP("SYSREG_ID_AA64MMFR2_EL1_TTL", NUM, 1), + MODEL_PROP("SYSREG_ID_AA64MMFR2_EL1_BBM", NUM, 2), + MODEL_PROP("SYSREG_ID_AA64MMFR2_EL1_EVT", NUM, 2), + MODEL_PROP("SYSREG_ID_AA64MMFR4_EL1_E2H0", NUM, 0), + + MODEL_PROP("SYSREG_CTR_EL0_IminLine", NUM, 4), + MODEL_PROP("SYSREG_CTR_EL0_L1Ip", NUM, 3), + MODEL_PROP("SYSREG_CTR_EL0_DminLine", NUM, 4), + MODEL_PROP("SYSREG_CTR_EL0_ERG", NUM, 4), + MODEL_PROP("SYSREG_CTR_EL0_CWG", NUM, 4), + + MODEL_PROP("SYSREG_DCZID_EL0_BS", NUM, 0x4), + + /* pauth */ + MODEL_PROP("SYSREG_ID_AA64ISAR1_EL1_APA", NUM, 5), + MODEL_PROP("SYSREG_ID_AA64ISAR1_EL1_GPA", NUM, 1), + + /* sve */ + MODEL_PROP("SYSREG_ID_AA64ZFR0_EL1_SVEver", NUM, 1), + MODEL_PROP("SYSREG_ID_AA64ZFR0_EL1_BF16", NUM, 1), + MODEL_PROP("SYSREG_ID_AA64ZFR0_EL1_BitPerm", NUM, 1), + MODEL_PROP("SYSREG_ID_AA64ZFR0_EL1_I8MM", NUM, 1), + MODEL_PROP("sve128", BOOL, true), + + MODEL_PROP_END, +}; + + +static const ArmModelPropValue grace_v1_props[] = { + MODEL_PROP("SYSREG_MIDR_EL1_Revision", NUM, 0x0), + + MODEL_PROP("SYSREG_ID_AA64ISAR0_EL1_AES", NUM, 2), + MODEL_PROP("SYSREG_ID_AA64ISAR0_EL1_SHA1", NUM, 1), + MODEL_PROP("SYSREG_ID_AA64ISAR0_EL1_SHA2", NUM, 2), + MODEL_PROP("SYSREG_ID_AA64ISAR0_EL1_SHA3", NUM, 1), + MODEL_PROP("SYSREG_ID_AA64ISAR0_EL1_SM3", NUM, 1), + MODEL_PROP("SYSREG_ID_AA64ISAR0_EL1_SM4", NUM, 1), + + MODEL_PROP("SYSREG_CTR_EL0_IDC", NUM, 1), + MODEL_PROP("SYSREG_CTR_EL0_DIC", NUM, 1), + + MODEL_PROP("SYSREG_REVIDR_EL1_VAL", NUM, 1), + + /* sve crypto (base sve inherited from neoverse-v2) */ + MODEL_PROP("SYSREG_ID_AA64ZFR0_EL1_AES", NUM, 2), + MODEL_PROP("SYSREG_ID_AA64ZFR0_EL1_SHA3", NUM, 1), + MODEL_PROP("SYSREG_ID_AA64ZFR0_EL1_SM4", NUM, 1), + + MODEL_PROP_END, +}; + static const ArmNamedCpuModel arm_cpu_models[] = { { .name = "non-zero-defaults-v1", @@ -218,6 +355,21 @@ static const ArmNamedCpuModel arm_cpu_models[] = { .parent = "neoverse-v1-v1", .props = graviton3_v1_props, }, + { + .name = "arm-v9_0-a-v1", + .parent = "arm-v8_4-a-v1", + .props = armv9_0_a_v1_props, + }, + { + .name = "neoverse-v2-v1", + .parent = "arm-v9_0-a-v1", + .props = neoverse_v2_v1_props, + }, + { + .name = "grace-v1", + .parent = "neoverse-v2-v1", + .props = grace_v1_props, + }, }; static ARMCPUInfo arm_named_cpu_infos[ARRAY_SIZE(arm_cpu_models)]; -- 2.52.0