[PATCH 15/17] target/arm: Pass MTEDESC to helper_dc_zva

Passing the mmu_idx and dcz blocksize in the descriptor is helpful,
as is unifying the helper interface with other DC insns.

Signed-off-by: Richard Henderson <[email protected]>
---
 target/arm/tcg/helper-a64-defs.h |  2 +-
 target/arm/tcg/mte_helper.c      |  6 +++---
 target/arm/tcg/translate-a64.c   | 21 ++++++++++++---------
 3 files changed, 16 insertions(+), 13 deletions(-)

diff --git a/target/arm/tcg/helper-a64-defs.h b/target/arm/tcg/helper-a64-defs.h
index 0e56e00f45..ac8f460ffb 100644
--- a/target/arm/tcg/helper-a64-defs.h
+++ b/target/arm/tcg/helper-a64-defs.h
@@ -80,7 +80,7 @@ DEF_HELPER_3(vfp_ah_maxh, f16, f16, f16, fpst)
 DEF_HELPER_3(vfp_ah_maxs, f32, f32, f32, fpst)
 DEF_HELPER_3(vfp_ah_maxd, f64, f64, f64, fpst)
 
-DEF_HELPER_FLAGS_2(dc_zva, TCG_CALL_NO_WG, void, env, i64)
+DEF_HELPER_FLAGS_3(dc_zva, TCG_CALL_NO_WG, void, env, i64, i32)
 
 DEF_HELPER_FLAGS_3(pacia, TCG_CALL_NO_WG, i64, env, i64, i64)
 DEF_HELPER_FLAGS_3(pacib, TCG_CALL_NO_WG, i64, env, i64, i64)
diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c
index 6e1f701c4c..4fa6066cbc 100644
--- a/target/arm/tcg/mte_helper.c
+++ b/target/arm/tcg/mte_helper.c
@@ -1117,11 +1117,11 @@ static void do_dczva_0(CPUARMState *env, vaddr addr, size_t len, void *mem,
     clear_helper_retaddr();
 }
 
-void HELPER(dc_zva)(CPUARMState *env, uint64_t addr)
+void HELPER(dc_zva)(CPUARMState *env, uint64_t addr, uint32_t desc)
 {
     uintptr_t ra = GETPC();
-    size_t len = (size_t)4 << get_dczid_bs(env_archcpu(env));
-    int mmu_idx = arm_env_mmu_index(env);
+    size_t len = FIELD_EX32(desc, MTEDESC, SIZEM1) + 1;
+    int mmu_idx = FIELD_EX32(desc, MTEDESC, MIDX);
     MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
     int flags;
     void *mem;
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 24a0cd8345..c3ff46989a 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -3137,14 +3137,16 @@ static void handle_sys(DisasContext *s, bool isread,
     }
     case ARM_CP_DC_ZVA:
         /* Writes clear the aligned block of memory which rt points into. */
-        if (s->mte_active[0]) {
-            tcg_rt = tcg_temp_new_i64();
-            gen_helper_mte_check_zva(tcg_rt, tcg_env, gen_mtedesc_zva(s),
-                                     cpu_reg(s, rt));
-        } else {
-            tcg_rt = cpu_reg(s, rt);
+        {
+            TCGv_i32 desc = gen_mtedesc_zva(s);
+            if (s->mte_active[0]) {
+                tcg_rt = tcg_temp_new_i64();
+                gen_helper_mte_check_zva(tcg_rt, tcg_env, desc, cpu_reg(s, rt));
+            } else {
+                tcg_rt = cpu_reg(s, rt);
+            }
+            gen_helper_dc_zva(tcg_env, tcg_rt, desc);
         }
-        gen_helper_dc_zva(tcg_env, tcg_rt);
         return;
     case ARM_CP_DC_GVA:
         {
@@ -3170,11 +3172,12 @@ static void handle_sys(DisasContext *s, bool isread,
     case ARM_CP_DC_GZVA:
         {
             TCGv_i64 clean_addr, tag;
+            TCGv_i32 desc = gen_mtedesc_zva(s);
 
             /* For DC_GZVA, we can rely on DC_ZVA for the proper fault. */
             tcg_rt = cpu_reg(s, rt);
             clean_addr = clean_data_tbi(s, tcg_rt);
-            gen_helper_dc_zva(tcg_env, clean_addr);
+            gen_helper_dc_zva(tcg_env, clean_addr, desc);
 
             if (s->ata[0]) {
                 /* Extract the tag from the register to match STZGM.  */
@@ -4788,7 +4791,7 @@ static bool trans_STZGM(DisasContext *s, arg_ldst_tag *a)
      * except the alignment happens before the access.
      */
     tcg_gen_andi_i64(addr, addr, -s->dcz_blocksize);
-    gen_helper_dc_zva(tcg_env, addr);
+    gen_helper_dc_zva(tcg_env, addr, gen_mtedesc_zva(s));
     return true;
 }
 
-- 
2.43.0