[RFC PATCH v2 100/137] hw/tricore: Give memory regions an explicit owner

Convert memory_region_init*() calls that pass NULL owner to pass
the enclosing machine or device instead.

Thread Object *owner through the static make_rom() / make_ram() / make_alias() helpers in tc27x_soc.c. All callers are inside tc27x_soc_init_memory_mapping(DeviceState *dev_soc).

No functional change intended.

RAMBlock idstrs are unchanged: the owners added here are Machine
or SysBus devices, and memory_region_register_ram() maps both to
dev=NULL for qemu_ram_set_idstr().

AI-used-for: code (refactoring)
Signed-off-by: Alexander Graf <[email protected]>
---
 hw/tricore/tc27x_soc.c         | 77 +++++++++++++++++-----------------
 hw/tricore/tricore_testboard.c | 12 +++---
 2 files changed, 45 insertions(+), 44 deletions(-)

diff --git a/hw/tricore/tc27x_soc.c b/hw/tricore/tc27x_soc.c
index 5b1b07cee1..0475698b29 100644
--- a/hw/tricore/tc27x_soc.c
+++ b/hw/tricore/tc27x_soc.c
@@ -67,10 +67,10 @@ const MemmapEntry tc27x_soc_memmap[] = {
  * Initialize the auxiliary ROM region @mr and map it into
  * the memory map at @base.
  */
-static void make_rom(MemoryRegion *mr, const char *name,
+static void make_rom(Object *owner, MemoryRegion *mr, const char *name,
                      hwaddr base, hwaddr size)
 {
-    memory_region_init_rom(mr, NULL, name, size, &error_fatal);
+    memory_region_init_rom(mr, owner, name, size, &error_fatal);
     memory_region_add_subregion(get_system_memory(), base, mr);
 }
 
@@ -78,10 +78,10 @@ static void make_rom(MemoryRegion *mr, const char *name,
  * Initialize the auxiliary RAM region @mr and map it into
  * the memory map at @base.
  */
-static void make_ram(MemoryRegion *mr, const char *name,
+static void make_ram(Object *owner, MemoryRegion *mr, const char *name,
                      hwaddr base, hwaddr size)
 {
-    memory_region_init_ram(mr, NULL, name, size, &error_fatal);
+    memory_region_init_ram(mr, owner, name, size, &error_fatal);
     memory_region_add_subregion(get_system_memory(), base, mr);
 }
 
@@ -89,10 +89,10 @@ static void make_ram(MemoryRegion *mr, const char *name,
  * Create an alias of an entire original MemoryRegion @orig
  * located at @base in the memory map.
  */
-static void make_alias(MemoryRegion *mr, const char *name,
+static void make_alias(Object *owner, MemoryRegion *mr, const char *name,
                            MemoryRegion *orig, hwaddr base)
 {
-    memory_region_init_alias(mr, NULL, name, orig, 0,
+    memory_region_init_alias(mr, owner, name, orig, 0,
                              memory_region_size(orig));
     memory_region_add_subregion(get_system_memory(), base, mr);
 }
@@ -101,81 +101,82 @@ static void tc27x_soc_init_memory_mapping(DeviceState *dev_soc)
 {
     TC27XSoCState *s = TC27X_SOC(dev_soc);
     TC27XSoCClass *sc = TC27X_SOC_GET_CLASS(s);
+    Object *obj = OBJECT(dev_soc);
 
-    make_ram(&s->cpu0mem.dspr, "CPU0.DSPR",
+    make_ram(obj, &s->cpu0mem.dspr, "CPU0.DSPR",
         sc->memmap[TC27XD_DSPR0].base, sc->memmap[TC27XD_DSPR0].size);
-    make_ram(&s->cpu0mem.pspr, "CPU0.PSPR",
+    make_ram(obj, &s->cpu0mem.pspr, "CPU0.PSPR",
         sc->memmap[TC27XD_PSPR0].base, sc->memmap[TC27XD_PSPR0].size);
-    make_ram(&s->cpu1mem.dspr, "CPU1.DSPR",
+    make_ram(obj, &s->cpu1mem.dspr, "CPU1.DSPR",
         sc->memmap[TC27XD_DSPR1].base, sc->memmap[TC27XD_DSPR1].size);
-    make_ram(&s->cpu1mem.pspr, "CPU1.PSPR",
+    make_ram(obj, &s->cpu1mem.pspr, "CPU1.PSPR",
         sc->memmap[TC27XD_PSPR1].base, sc->memmap[TC27XD_PSPR1].size);
-    make_ram(&s->cpu2mem.dspr, "CPU2.DSPR",
+    make_ram(obj, &s->cpu2mem.dspr, "CPU2.DSPR",
         sc->memmap[TC27XD_DSPR2].base, sc->memmap[TC27XD_DSPR2].size);
-    make_ram(&s->cpu2mem.pspr, "CPU2.PSPR",
+    make_ram(obj, &s->cpu2mem.pspr, "CPU2.PSPR",
         sc->memmap[TC27XD_PSPR2].base, sc->memmap[TC27XD_PSPR2].size);
 
     /* TODO: Control Cache mapping with Memory Test Unit (MTU) */
-    make_ram(&s->cpu2mem.dcache, "CPU2.DCACHE",
+    make_ram(obj, &s->cpu2mem.dcache, "CPU2.DCACHE",
         sc->memmap[TC27XD_DCACHE2].base, sc->memmap[TC27XD_DCACHE2].size);
-    make_ram(&s->cpu2mem.dtag,   "CPU2.DTAG",
+    make_ram(obj, &s->cpu2mem.dtag,   "CPU2.DTAG",
         sc->memmap[TC27XD_DTAG2].base, sc->memmap[TC27XD_DTAG2].size);
-    make_ram(&s->cpu2mem.pcache, "CPU2.PCACHE",
+    make_ram(obj, &s->cpu2mem.pcache, "CPU2.PCACHE",
         sc->memmap[TC27XD_PCACHE2].base, sc->memmap[TC27XD_PCACHE2].size);
-    make_ram(&s->cpu2mem.ptag,   "CPU2.PTAG",
+    make_ram(obj, &s->cpu2mem.ptag,   "CPU2.PTAG",
         sc->memmap[TC27XD_PTAG2].base, sc->memmap[TC27XD_PTAG2].size);
 
-    make_ram(&s->cpu1mem.dcache, "CPU1.DCACHE",
+    make_ram(obj, &s->cpu1mem.dcache, "CPU1.DCACHE",
         sc->memmap[TC27XD_DCACHE1].base, sc->memmap[TC27XD_DCACHE1].size);
-    make_ram(&s->cpu1mem.dtag,   "CPU1.DTAG",
+    make_ram(obj, &s->cpu1mem.dtag,   "CPU1.DTAG",
         sc->memmap[TC27XD_DTAG1].base, sc->memmap[TC27XD_DTAG1].size);
-    make_ram(&s->cpu1mem.pcache, "CPU1.PCACHE",
+    make_ram(obj, &s->cpu1mem.pcache, "CPU1.PCACHE",
         sc->memmap[TC27XD_PCACHE1].base, sc->memmap[TC27XD_PCACHE1].size);
-    make_ram(&s->cpu1mem.ptag,   "CPU1.PTAG",
+    make_ram(obj, &s->cpu1mem.ptag,   "CPU1.PTAG",
         sc->memmap[TC27XD_PTAG1].base, sc->memmap[TC27XD_PTAG1].size);
 
-    make_ram(&s->cpu0mem.pcache, "CPU0.PCACHE",
+    make_ram(obj, &s->cpu0mem.pcache, "CPU0.PCACHE",
         sc->memmap[TC27XD_PCACHE0].base, sc->memmap[TC27XD_PCACHE0].size);
-    make_ram(&s->cpu0mem.ptag,   "CPU0.PTAG",
+    make_ram(obj, &s->cpu0mem.ptag,   "CPU0.PTAG",
         sc->memmap[TC27XD_PTAG0].base, sc->memmap[TC27XD_PTAG0].size);
 
     /*
      * TriCore QEMU executes CPU0 only, thus it is sufficient to map
      * LOCAL.PSPR/LOCAL.DSPR exclusively onto PSPR0/DSPR0.
      */
-    make_alias(&s->psprX, "LOCAL.PSPR", &s->cpu0mem.pspr,
+    make_alias(obj, &s->psprX, "LOCAL.PSPR", &s->cpu0mem.pspr,
         sc->memmap[TC27XD_PSPRX].base);
-    make_alias(&s->dsprX, "LOCAL.DSPR", &s->cpu0mem.dspr,
+    make_alias(obj, &s->dsprX, "LOCAL.DSPR", &s->cpu0mem.dspr,
         sc->memmap[TC27XD_DSPRX].base);
 
-    make_ram(&s->flashmem.pflash0_c, "PF0",
+    make_ram(obj, &s->flashmem.pflash0_c, "PF0",
         sc->memmap[TC27XD_PFLASH0_C].base, sc->memmap[TC27XD_PFLASH0_C].size);
-    make_ram(&s->flashmem.pflash1_c, "PF1",
+    make_ram(obj, &s->flashmem.pflash1_c, "PF1",
         sc->memmap[TC27XD_PFLASH1_C].base, sc->memmap[TC27XD_PFLASH1_C].size);
-    make_ram(&s->flashmem.dflash0,   "DF0",
+    make_ram(obj, &s->flashmem.dflash0,   "DF0",
         sc->memmap[TC27XD_DFLASH0].base, sc->memmap[TC27XD_DFLASH0].size);
-    make_ram(&s->flashmem.dflash1,   "DF1",
+    make_ram(obj, &s->flashmem.dflash1,   "DF1",
         sc->memmap[TC27XD_DFLASH1].base, sc->memmap[TC27XD_DFLASH1].size);
-    make_ram(&s->flashmem.olda_c,    "OLDA",
+    make_ram(obj, &s->flashmem.olda_c,    "OLDA",
         sc->memmap[TC27XD_OLDA_C].base, sc->memmap[TC27XD_OLDA_C].size);
-    make_rom(&s->flashmem.brom_c,    "BROM",
+    make_rom(obj, &s->flashmem.brom_c,    "BROM",
         sc->memmap[TC27XD_BROM_C].base, sc->memmap[TC27XD_BROM_C].size);
-    make_ram(&s->flashmem.lmuram_c,  "LMURAM",
+    make_ram(obj, &s->flashmem.lmuram_c,  "LMURAM",
         sc->memmap[TC27XD_LMURAM_C].base, sc->memmap[TC27XD_LMURAM_C].size);
-    make_ram(&s->flashmem.emem_c,    "EMEM",
+    make_ram(obj, &s->flashmem.emem_c,    "EMEM",
         sc->memmap[TC27XD_EMEM_C].base, sc->memmap[TC27XD_EMEM_C].size);
 
-    make_alias(&s->flashmem.pflash0_u, "PF0.U",    &s->flashmem.pflash0_c,
+    make_alias(obj, &s->flashmem.pflash0_u, "PF0.U",    &s->flashmem.pflash0_c,
         sc->memmap[TC27XD_PFLASH0_U].base);
-    make_alias(&s->flashmem.pflash1_u, "PF1.U",    &s->flashmem.pflash1_c,
+    make_alias(obj, &s->flashmem.pflash1_u, "PF1.U",    &s->flashmem.pflash1_c,
         sc->memmap[TC27XD_PFLASH1_U].base);
-    make_alias(&s->flashmem.olda_u,    "OLDA.U",   &s->flashmem.olda_c,
+    make_alias(obj, &s->flashmem.olda_u,    "OLDA.U",   &s->flashmem.olda_c,
         sc->memmap[TC27XD_OLDA_U].base);
-    make_alias(&s->flashmem.brom_u,    "BROM.U",   &s->flashmem.brom_c,
+    make_alias(obj, &s->flashmem.brom_u,    "BROM.U",   &s->flashmem.brom_c,
         sc->memmap[TC27XD_BROM_U].base);
-    make_alias(&s->flashmem.lmuram_u,  "LMURAM.U", &s->flashmem.lmuram_c,
+    make_alias(obj, &s->flashmem.lmuram_u,  "LMURAM.U", &s->flashmem.lmuram_c,
         sc->memmap[TC27XD_LMURAM_U].base);
-    make_alias(&s->flashmem.emem_u,    "EMEM.U",   &s->flashmem.emem_c,
+    make_alias(obj, &s->flashmem.emem_u,    "EMEM.U",   &s->flashmem.emem_c,
         sc->memmap[TC27XD_EMEM_U].base);
 }
 
diff --git a/hw/tricore/tricore_testboard.c b/hw/tricore/tricore_testboard.c
index 9e8cccbd59..4b5398ab95 100644
--- a/hw/tricore/tricore_testboard.c
+++ b/hw/tricore/tricore_testboard.c
@@ -70,17 +70,17 @@ static void tricore_testboard_init(MachineState *machine, int board_id)
 
     cpu = TRICORE_CPU(cpu_create(mo, "cpu", machine->cpu_type));
     env = &cpu->env;
-    memory_region_init_ram(ext_cram, NULL, "powerlink_ext_c.ram",
+    memory_region_init_ram(ext_cram, OBJECT(machine), "powerlink_ext_c.ram",
                            2 * MiB, &error_fatal);
-    memory_region_init_ram(ext_dram, NULL, "powerlink_ext_d.ram",
+    memory_region_init_ram(ext_dram, OBJECT(machine), "powerlink_ext_d.ram",
                            4 * MiB, &error_fatal);
-    memory_region_init_ram(int_cram, NULL, "powerlink_int_c.ram", 48 * KiB,
+    memory_region_init_ram(int_cram, OBJECT(machine), "powerlink_int_c.ram", 48 * KiB,
                            &error_fatal);
-    memory_region_init_ram(int_dram, NULL, "powerlink_int_d.ram", 48 * KiB,
+    memory_region_init_ram(int_dram, OBJECT(machine), "powerlink_int_d.ram", 48 * KiB,
                            &error_fatal);
-    memory_region_init_ram(pcp_data, NULL, "powerlink_pcp_data.ram",
+    memory_region_init_ram(pcp_data, OBJECT(machine), "powerlink_pcp_data.ram",
                            16 * KiB, &error_fatal);
-    memory_region_init_ram(pcp_text, NULL, "powerlink_pcp_text.ram",
+    memory_region_init_ram(pcp_text, OBJECT(machine), "powerlink_pcp_text.ram",
                            32 * KiB, &error_fatal);
 
     memory_region_add_subregion(sysmem, 0x80000000, ext_cram);
-- 
2.47.1