Re: [RFC PATCH v6 08/17] target/arm/cpu-idregs.h.inc: Generate enum values

Eric Auger <[email protected]>
Newsgroups org.nongnu.qemu-arm,dev.linux.lists.kvmarm,org.nongnu.qemu-devel
Message-ID <[email protected]>
Hi Kushit,

On 6/19/26 8:28 AM, Khushit Shah wrote:
> From f0e489cebdac1ba94b8082bc240f2d889555f7ea Mon Sep 17 00:00:00 2001
> From: Khushit Shah <[email protected]>
> Date: Fri, 19 Jun 2026 11:54:29 +0530
> Subject: [PATCH] scripts: bug fixes in update-aarch64-cpu-sysreg-properties
>
> Signed-off-by: Khushit Shah <[email protected]>
> ---
> While rebasing I found two bugs here:
> - It outputs incorrect value for field that defined a ValueRange.
>    For example, CTX_CMPs (and all similar fields).
I attached the diff it generates. I am not sure this is exactly what we
want. 

for ValueRange such as SMIDR_EL1.HIP

                          "_type": "Values.ValueRange",
                          "end": {
                            "_type": "Values.Value",
                            "meaning": null,
                            "value": "'1111'"
                          },
                          "meaning": null,
                          "start": {
                            "_type": "Values.Value",
                            "meaning": null,
                            "value": "'0001'"

I guess you want all values between 1 and 15
whereas the script currently generates a single value.

Also in the diff I don't see any wrong parsing of 

"decimal 10 might be incorrectly parsed as to 2" fixed by the script. Nevertheless can be a proper issue

Thanks

Eric

> - decimal 10 might be incorrectly parsed as to 2.
>
> Sending inline patch that I have added.
> ---
>  .../update-aarch64-cpu-sysreg-properties.py   | 56 ++++++++++++-------
>  1 file changed, 35 insertions(+), 21 deletions(-)
>  mode change 100644 => 100755 scripts/update-aarch64-cpu-sysreg-properties.py
>
> diff --git a/scripts/update-aarch64-cpu-sysreg-properties.py b/scripts/update-aarch64-cpu-sysreg-properties.py
> old mode 100644
> new mode 100755
> index 9e829fda2e..2e28b03598
> --- a/scripts/update-aarch64-cpu-sysreg-properties.py
> +++ b/scripts/update-aarch64-cpu-sysreg-properties.py
> @@ -106,6 +106,29 @@ def collect_fields(item, bit_offset=0):
>  
>      return fields
>  
> +def parse_value_int(raw_val):
> +    if raw_val is None or isinstance(raw_val, bool):
> +        return None
> +
> +    # may already be real number
> +    if isinstance(raw_val, int):
> +        return raw_val
> +
> +    raw_str = str(raw_val).strip()
> +
> +    if "'" in raw_str:
> +        # quoted bitstring like "'0100'"
> +        bits = raw_str.replace("'", "")
> +        try:
> +            return int(bits, 2)
> +        except ValueError:
> +            return None
> +
> +    # unquoted, try decimal
> +    try:
> +        return int(raw_str, 0)
> +    except ValueError:
> +        return None
>  
>  def extract_field_enums(field):
>      enums = []
> @@ -124,32 +147,23 @@ def extract_field_enums(field):
>      if not isinstance(val_entries, list):
>          return enums
>  
> +    # A Values.ValueRange field specifies start and end value for a range.
> +    # Don't enumerate anything for them.
> +    for val_entry in val_entries:
> +        if isinstance(val_entry, dict) and \
> +           val_entry.get("_type") == "Values.ValueRange":
> +               return []
> +
>      for val_entry in val_entries:
>          if not isinstance(val_entry, dict):
>              continue
> -            
> +
>          if val_entry.get("_type") == "Values.Value":
> -            raw_val = val_entry.get("value")
> -            if raw_val is None:
> +            int_val = parse_value_int(val_entry.get("value"))
> +            if int_val is None:
>                  continue
> -                
> -            # some of the values have ' like "'0100'"
> -            raw_val_str = str(raw_val).strip().replace("'", "")
> -            
> -            try:
> -                # convert into bin 
> -                int_val = int(raw_val_str, 2)
> -            except ValueError:
> -                try:
> -                    # Fallback to dec if not bin
> -                    int_val = int(raw_val_str, 0)
> -                except ValueError:
> -                    continue
> -            
> -            enums.append({
> -                'value': int_val
> -            })
> -            
> +            enums.append({'value': int_val})
> +
>      return enums
>  
>  def generate_sysreg_properties_from_registers_json(id_reg_names, raw_json_path):
> --
> 2.52.0
>
>
>
cpu-idregs.h.inc.diff (text/x-patch, 2.2 KB)
--- target/arm/cpu-idregs.h.inc	2026-07-20 14:44:43.174603741 +0200
+++ target/arm/cpu-idregs.h.inc.red	2026-07-20 14:44:07.917890712 +0200
@@ -133,13 +133,17 @@
         IDREG_FIELD_ARCH_VAL(5)
         IDREG_FIELD_ARCH_VAL(6)
     IDREG_FIELD_END(ID_AA64DFR0_EL1, PMSVer)
-    IDREG_FIELD(ID_AA64DFR0_EL1, CTX_CMPs, 28, 4)
+    IDREG_FIELD_START(ID_AA64DFR0_EL1, CTX_CMPs, 28, 4)
+        IDREG_FIELD_ARCH_VAL(15)
+    IDREG_FIELD_END(ID_AA64DFR0_EL1, CTX_CMPs)
     IDREG_FIELD(ID_AA64DFR0_EL1, WRPs, 20, 4)
     IDREG_FIELD_START(ID_AA64DFR0_EL1, PMSS, 16, 4)
         IDREG_FIELD_ARCH_VAL(0)
         IDREG_FIELD_ARCH_VAL(1)
     IDREG_FIELD_END(ID_AA64DFR0_EL1, PMSS)
-    IDREG_FIELD(ID_AA64DFR0_EL1, BRPs, 12, 4)
+    IDREG_FIELD_START(ID_AA64DFR0_EL1, BRPs, 12, 4)
+        IDREG_FIELD_ARCH_VAL(15)
+    IDREG_FIELD_END(ID_AA64DFR0_EL1, BRPs)
     IDREG_FIELD_START(ID_AA64DFR0_EL1, PMUVer, 8, 4)
         IDREG_FIELD_ARCH_VAL(0)
         IDREG_FIELD_ARCH_VAL(1)
@@ -192,9 +196,15 @@
         IDREG_FIELD_ARCH_VAL(1)
         IDREG_FIELD_ARCH_VAL(2)
     IDREG_FIELD_END(ID_AA64DFR1_EL1, SPMU)
-    IDREG_FIELD(ID_AA64DFR1_EL1, CTX_CMPs, 24, 8)
-    IDREG_FIELD(ID_AA64DFR1_EL1, WRPs, 16, 8)
-    IDREG_FIELD(ID_AA64DFR1_EL1, BRPs, 8, 8)
+    IDREG_FIELD_START(ID_AA64DFR1_EL1, CTX_CMPs, 24, 8)
+        IDREG_FIELD_ARCH_VAL(0)
+    IDREG_FIELD_END(ID_AA64DFR1_EL1, CTX_CMPs)
+    IDREG_FIELD_START(ID_AA64DFR1_EL1, WRPs, 16, 8)
+        IDREG_FIELD_ARCH_VAL(0)
+    IDREG_FIELD_END(ID_AA64DFR1_EL1, WRPs)
+    IDREG_FIELD_START(ID_AA64DFR1_EL1, BRPs, 8, 8)
+        IDREG_FIELD_ARCH_VAL(0)
+    IDREG_FIELD_END(ID_AA64DFR1_EL1, BRPs)
     IDREG_FIELD(ID_AA64DFR1_EL1, SYSPMUID, 0, 8)
 IDREG_END(ID_AA64DFR1_EL1)
 
@@ -2049,8 +2059,13 @@
 IDREG_END(REVIDR_EL1)
 
 IDREG_START(SMIDR_EL1)
-    IDREG_FIELD(SMIDR_EL1, NSMC, 56, 4)
-    IDREG_FIELD(SMIDR_EL1, HIP, 52, 4)
+    IDREG_FIELD_START(SMIDR_EL1, NSMC, 56, 4)
+        IDREG_FIELD_ARCH_VAL(0)
+        IDREG_FIELD_ARCH_VAL(15)
+    IDREG_FIELD_END(SMIDR_EL1, NSMC)
+    IDREG_FIELD_START(SMIDR_EL1, HIP, 52, 4)
+        IDREG_FIELD_ARCH_VAL(0)
+    IDREG_FIELD_END(SMIDR_EL1, HIP)
     IDREG_FIELD(SMIDR_EL1, Affinity2, 32, 20)
     IDREG_FIELD_START(SMIDR_EL1, Implementer, 24, 8)
         IDREG_FIELD_ARCH_VAL(0)
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