Re: [PATCH 12/17] target/arm: Split out helpers for creating MTEDESC

On 7/20/26 01:35, Philippe Mathieu-Daudé wrote:
> On 18/7/26 01:23, Richard Henderson wrote:
>> Assert that align and size values fit in their fields.
>> This results in more fields being filled than some
>> helpers actually use, but uniformity is for the best.
>>
>> Signed-off-by: Richard Henderson <[email protected]>
>> ---
>>   target/arm/tcg/translate-a64.c | 123 ++++++++++++++++-----------------
>>   1 file changed, 58 insertions(+), 65 deletions(-)
> 
> 
>> +static TCGv_i32 gen_mtedesc_xas(DisasContext *s, bool write, int idx,
>> +                                unsigned align, unsigned size)
>> +{
>> +    int desc = 0;
>> +
>> +    desc = FIELD_DP32(desc, MTEDESC, MIDX, idx);
>> +    desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid);
>> +    desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma);
>> +    desc = FIELD_DP32(desc, MTEDESC, WRITE, write);
>> +    desc = FIELD_DP32(desc, MTEDESC, ALIGN, align);
>> +    desc = FIELD_DP32(desc, MTEDESC, MTX, s->mtx);
>> +    desc = FIELD_DP32(desc, MTEDESC, SIZEM1, size - 1);
>> +
>> +    assert(FIELD_EX32(desc, MTEDESC, ALIGN) == align);
>> +    assert(FIELD_EX32(desc, MTEDESC, SIZEM1) == size - 1);
> 
> Why assert? This can't happen...

It's not impossible: this is a bitfield smaller than 'unsigned', and it'll also catch size 
== 0.  The largest use so far is 512 for user-mode DC_ZVA, 9 bits, and we currently 
allocate 18 bits to this field.  It's just about future-proofing.


r~