[PATCH v6 04/11] hw/arm/ast27x0: Add DRAM alias for SSP SDRAM remap

This commit adds two MemoryRegion aliases to support PSP access to
SSP SDRAM through shared memory remapping.

The SSP exposes two DRAM aliases:
  - remap1 maps PSP DRAM at 0x400000000 to SSP SDRAM offset 0x5880000
  - remap2 maps PSP DRAM at 0x42C000000 to SSP SDRAM offset 0x0

These mappings follow the default SCU register configuration used by
the ASPEED SDK firmware, which defines the memory window mapping
between PSP and the SSP.

The alias MemoryRegions belong to the SSP coprocessor state itself
(Aspeed27x0CoprocessorState), since that is what they represent; the
SCU only holds pointers to them (ssp_remap[0]/ssp_remap[1]) so its
control registers can reposition/resize the aliases at runtime. These
can't be QOM link properties since the SCU is already realized by the
time the SSP sets them, so the pointers are written in directly.

The SSP cpu_index is only known once the SSP's armv7m core is
realized, so it is written directly into the shared SCU at that
point. Its "not wired up" default of -1 is now set explicitly in the
SCU's own realize(), since nothing else sets it via a QOM property
anymore.

Signed-off-by: Jamin Lin <[email protected]>
Tested-by: Philippe Mathieu-Daudé <[email protected]>
---
 include/hw/arm/aspeed_coprocessor.h |  2 ++
 include/hw/misc/aspeed_scu.h        |  3 +++
 hw/arm/aspeed_ast27x0-fc.c          |  2 ++
 hw/arm/aspeed_ast27x0-ssp.c         | 38 +++++++++++++++++++++++++++++
 hw/misc/aspeed_scu.c                |  3 +++
 5 files changed, 48 insertions(+)

diff --git a/include/hw/arm/aspeed_coprocessor.h b/include/hw/arm/aspeed_coprocessor.h
index 23c3b97f06..d9d0ae7b6d 100644
--- a/include/hw/arm/aspeed_coprocessor.h
+++ b/include/hw/arm/aspeed_coprocessor.h
@@ -52,6 +52,8 @@ struct Aspeed27x0CoprocessorState {
     MemoryRegion scu_alias;
     MemoryRegion scuio_alias;
     MemoryRegion fmc_alias;
+    MemoryRegion dram_remap[2];
+    MemoryRegion *dram;
     Aspeed2700SCUState *scu;
     AspeedSCUState *scuio;
     AspeedSMCState *fmc;
diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h
index 904549465f..01e8854104 100644
--- a/include/hw/misc/aspeed_scu.h
+++ b/include/hw/misc/aspeed_scu.h
@@ -44,6 +44,9 @@ struct AspeedSCUState {
 
 struct Aspeed2700SCUState {
     AspeedSCUState parent_obj;
+
+    MemoryRegion *ssp_remap[2];
+    int ssp_cpuid;
 };
 
 #define AST2400_A1_SILICON_REV   0x02010303U
diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c
index 058cea42ed..af700e748f 100644
--- a/hw/arm/aspeed_ast27x0-fc.c
+++ b/hw/arm/aspeed_ast27x0-fc.c
@@ -155,6 +155,8 @@ static bool ast2700fc_ssp_init(Ast2700FCState *s, AspeedSoCState *psp,
                             &error_abort);
     object_property_set_link(OBJECT(&s->ssp), "sram",
                              OBJECT(&psp->sram), &error_abort);
+    object_property_set_link(OBJECT(&s->ssp), "dram",
+                             OBJECT(psp->dram_mr), &error_abort);
     object_property_set_link(OBJECT(&s->ssp), "scu",
                              OBJECT(&s->ca35.scu), &error_abort);
     object_property_set_link(OBJECT(&s->ssp), "scuio",
diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c
index 9c984d23cd..2b0cf5041f 100644
--- a/hw/arm/aspeed_ast27x0-ssp.c
+++ b/hw/arm/aspeed_ast27x0-ssp.c
@@ -184,6 +184,12 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)
         return;
     }
 
+    if (!a->dram) {
+        error_setg(errp, TYPE_ASPEED27X0SSP_COPROCESSOR
+                   ": 'dram' link is not set");
+        return;
+    }
+
     /* AST27X0 SSP Core */
     armv7m = DEVICE(&a->armv7m);
     qdev_prop_set_uint32(armv7m, "num-irq", 256);
@@ -201,6 +207,12 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)
                              &error_abort);
     sysbus_realize(SYS_BUS_DEVICE(&a->armv7m), &error_abort);
 
+    /*
+     * cpu_index is only known once the armv7m core above is realized;
+     * write it directly into the shared SCU.
+     */
+    a->scu->ssp_cpuid = CPU(a->armv7m.cpu)->cpu_index;
+
     /* SDRAM */
     sdram_name = g_strdup_printf("aspeed.sdram.%d",
                                  CPU(a->armv7m.cpu)->cpu_index);
@@ -232,6 +244,30 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)
     memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SCUIO],
                                 &a->scuio_alias);
 
+    /*
+     * DRAM remap aliases used by PSP to access SSP SDRAM:
+     * - remap[0] maps PSP DRAM at 0x400000000 (size: 0x1A77E000) to
+     *   SSP SDRAM offset 0x5880000
+     * - remap[1] maps PSP DRAM at 0x42C000000 (size: 0x05880000) to
+     *   SSP SDRAM offset 0x0
+     */
+    memory_region_init_alias(&a->dram_remap[0], OBJECT(a), "ssp.dram.remap1",
+                             a->dram, 0, 0x1a77e000);
+    memory_region_init_alias(&a->dram_remap[1], OBJECT(a), "ssp.dram.remap2",
+                             a->dram, 0x2c000000, 0x05880000);
+    memory_region_add_subregion(&s->sdram, 0, &a->dram_remap[1]);
+    memory_region_add_subregion(&s->sdram,
+                                memory_region_size(&a->dram_remap[1]),
+                                &a->dram_remap[0]);
+
+    /*
+     * The SCU is already realized at this point (it belongs to the PSP,
+     * which is realized before the SSP), so the remaps are linked in
+     * directly instead of via QOM properties.
+     */
+    a->scu->ssp_remap[0] = &a->dram_remap[0];
+    a->scu->ssp_remap[1] = &a->dram_remap[1];
+
     /* INTC */
     if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[0]), errp)) {
         return;
@@ -317,6 +353,8 @@ static const Property aspeed_27x0_coprocessor_properties[] = {
                      TYPE_ASPEED_SCU, AspeedSCUState *),
     DEFINE_PROP_LINK("fmc", Aspeed27x0CoprocessorState, fmc, TYPE_ASPEED_SMC,
                      AspeedSMCState *),
+    DEFINE_PROP_LINK("dram", Aspeed27x0CoprocessorState, dram,
+                     TYPE_MEMORY_REGION, MemoryRegion *),
 };
 
 static void aspeed_soc_ast27x0ssp_class_init(ObjectClass *klass,
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index ca93c3699d..4025ea3205 100644
--- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c
@@ -932,6 +932,9 @@ static void aspeed_ast2700_scu_reset_hold(Object *obj, ResetType type)
 
 static void aspeed_2700_scu_realize(DeviceState *dev, Error **errp)
 {
+    Aspeed2700SCUState *a = ASPEED_2700_SCU(dev);
+
+    a->ssp_cpuid = -1;
     aspeed_scu_realize(dev, errp);
 }
 
-- 
2.43.0