[PATCH v6 05/11] hw/arm/ast27x0: Add DRAM alias for TSP SDRAM remap

This commit adds a MemoryRegion alias to support PSP access to
TSP SDRAM through shared memory remapping.

The TSP coprocessor exposes one DRAM alias:
- remap maps PSP DRAM at 0x42E000000 to TSP SDRAM offset 0x0

These mappings follow the default SCU register configuration used by
the ASPEED SDK firmware, which defines the memory window mapping
between PSP and TSP.

The alias MemoryRegion belongs to the TSP coprocessor state itself
(Aspeed27x0CoprocessorState), mirroring the SSP remap; the SCU only
holds a pointer to it (tsp_remap) so its control registers can
reposition/resize the alias at runtime. This can't be a QOM link
property since the SCU is already realized by the time the TSP sets
it, so the pointer is written in directly.

The TSP cpu_index is only known once the TSP's armv7m core is
realized, so it is written directly into the shared SCU at that
point. Its "not wired up" default of -1 is now set explicitly in the
SCU's own realize(), since nothing else sets it via a QOM property
anymore.

Signed-off-by: Jamin Lin <[email protected]>
Tested-by: Philippe Mathieu-Daudé <[email protected]>
---
 include/hw/misc/aspeed_scu.h |  2 ++
 hw/arm/aspeed_ast27x0-fc.c   |  2 ++
 hw/arm/aspeed_ast27x0-tsp.c  | 30 ++++++++++++++++++++++++++++++
 hw/misc/aspeed_scu.c         |  1 +
 4 files changed, 35 insertions(+)

diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h
index 01e8854104..aef13e8915 100644
--- a/include/hw/misc/aspeed_scu.h
+++ b/include/hw/misc/aspeed_scu.h
@@ -46,7 +46,9 @@ struct Aspeed2700SCUState {
     AspeedSCUState parent_obj;
 
     MemoryRegion *ssp_remap[2];
+    MemoryRegion *tsp_remap;
     int ssp_cpuid;
+    int tsp_cpuid;
 };
 
 #define AST2400_A1_SILICON_REV   0x02010303U
diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c
index af700e748f..e51d8024eb 100644
--- a/hw/arm/aspeed_ast27x0-fc.c
+++ b/hw/arm/aspeed_ast27x0-fc.c
@@ -191,6 +191,8 @@ static bool ast2700fc_tsp_init(Ast2700FCState *s, AspeedSoCState *psp,
                             &error_abort);
     object_property_set_link(OBJECT(&s->tsp), "sram",
                              OBJECT(&psp->sram), &error_abort);
+    object_property_set_link(OBJECT(&s->tsp), "dram",
+                             OBJECT(psp->dram_mr), &error_abort);
     object_property_set_link(OBJECT(&s->tsp), "scu",
                              OBJECT(&s->ca35.scu), &error_abort);
     object_property_set_link(OBJECT(&s->tsp), "scuio",
diff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c
index 4212e7bd4c..9a860f6ea3 100644
--- a/hw/arm/aspeed_ast27x0-tsp.c
+++ b/hw/arm/aspeed_ast27x0-tsp.c
@@ -184,6 +184,12 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error **errp)
         return;
     }
 
+    if (!a->dram) {
+        error_setg(errp, TYPE_ASPEED27X0TSP_COPROCESSOR
+                   ": 'dram' link is not set");
+        return;
+    }
+
     /* AST27X0 TSP Core */
     armv7m = DEVICE(&a->armv7m);
     qdev_prop_set_uint32(armv7m, "num-irq", 256);
@@ -201,6 +207,12 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error **errp)
                              &error_abort);
     sysbus_realize(SYS_BUS_DEVICE(&a->armv7m), &error_abort);
 
+    /*
+     * cpu_index is only known once the armv7m core above is realized;
+     * write it directly into the shared SCU.
+     */
+    a->scu->tsp_cpuid = CPU(a->armv7m.cpu)->cpu_index;
+
     /* SDRAM */
     sdram_name = g_strdup_printf("aspeed.sdram.%d",
                                  CPU(a->armv7m.cpu)->cpu_index);
@@ -232,6 +244,22 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error **errp)
     memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SCUIO],
                                 &a->scuio_alias);
 
+    /*
+     * DRAM remap alias used by PSP to access TSP SDRAM:
+     * - remap maps PSP DRAM at 0x42E000000 (size: 32MB) to TSP SDRAM
+     *   offset 0x0
+     */
+    memory_region_init_alias(&a->dram_remap[0], OBJECT(a), "tsp.dram.remap",
+                             a->dram, 0x2e000000, 32 * MiB);
+    memory_region_add_subregion(&s->sdram, 0, &a->dram_remap[0]);
+
+    /*
+     * The SCU is already realized at this point (it belongs to the PSP,
+     * which is realized before the TSP), so the remap is linked in
+     * directly instead of via a QOM property.
+     */
+    a->scu->tsp_remap = &a->dram_remap[0];
+
     /* INTC */
     if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[0]), errp)) {
         return;
@@ -317,6 +345,8 @@ static const Property aspeed_27x0_coprocessor_properties[] = {
                      TYPE_ASPEED_SCU, AspeedSCUState *),
     DEFINE_PROP_LINK("fmc", Aspeed27x0CoprocessorState, fmc, TYPE_ASPEED_SMC,
                      AspeedSMCState *),
+    DEFINE_PROP_LINK("dram", Aspeed27x0CoprocessorState, dram,
+                     TYPE_MEMORY_REGION, MemoryRegion *),
 };
 
 static void aspeed_soc_ast27x0tsp_class_init(ObjectClass *klass,
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index 4025ea3205..5d34dbea5e 100644
--- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c
@@ -935,6 +935,7 @@ static void aspeed_2700_scu_realize(DeviceState *dev, Error **errp)
     Aspeed2700SCUState *a = ASPEED_2700_SCU(dev);
 
     a->ssp_cpuid = -1;
+    a->tsp_cpuid = -1;
     aspeed_scu_realize(dev, errp);
 }
 
-- 
2.43.0