Re: [PATCH] hw/misc/mps2-scc.c: fix scc_partno() and cfg7 write

On Thu, 23 Jul 2026 at 17:43, Simon Xu <[email protected]> wrote:
>
> Increase the extract32 length from 8 to 12. The Primary part number is
> defined as bits[15:4] by the "SSE-310 with M85 and U55 FPGA"
> documentation. For example for the mps3-an547, 0x547 is 12 bits but we
> only return 8 bits right now.
>
> Change the CFG7 write function to modify the correct variable.
>
> Signed-off-by: Simon Xu <[email protected]>
> ---
>  hw/misc/mps2-scc.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c
> index 7877b31479..554b504c72 100644
> --- a/hw/misc/mps2-scc.c
> +++ b/hw/misc/mps2-scc.c
> @@ -57,7 +57,7 @@ REG32(ID, 0xFFC)
>  static int scc_partno(MPS2SCC *s)
>  {
>      /* Return the partno field of the SCC_ID (0x524, 0x511, etc) */
> -    return extract32(s->id, 4, 8);
> +    return extract32(s->id, 4, 12);
>  }

Whoops, this is in "how did this ever work?" territory. I
guess most guests don't actually do enough with the
part-specific bits of the device to notice...

>
>  /* Is CFG_REG2 present? */
> @@ -299,7 +299,7 @@ static void mps2_scc_write(void *opaque, hwaddr offset, uint64_t value,
>              goto bad_offset;
>          }
>          /* AN536: Core 1 vector table base address */
> -        s->cfg6 = value;
> +        s->cfg7 = value;
>          break;


This is also an obvious cut-and-paste bug: writing to A_CFG7
should clearly write s->cfg7, not 6.

However, these are two separate unrelated bugs. Could you send
them as two separate patches, please? (You can put them in a
2-patch series with a cover letter.)

thanks
-- PMM