[PATCH 09/11] tcg/aarch64: Implement revbit{32,64}
Richard Henderson <[email protected]> Thu, 30 Jul 2026 17:05:01 -0700
| Newsgroups | org.nongnu.qemu-arm,org.nongnu.qemu-devel |
|---|---|
| Message-ID | <[email protected]> |
Signed-off-by: Richard Henderson <[email protected]> --- tcg/aarch64/tcg-target.c.inc | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index aa2c4e42ed..2622f89880 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -2652,12 +2652,28 @@ static const TCGOutOpUnary outop_bswap64 = { .out_rr = tgen_bswap64, }; +static void tgen_revbit32(TCGContext *s, TCGType type, + TCGReg a0, TCGReg a1, unsigned flags) +{ + tcg_out_insn(s, rr_sf, RBIT, TCG_TYPE_I32, a0, a1); + if (flags & TCG_BSWAP_OS) { + tcg_out_ext32s(s, a0, a0); + } +} + static const TCGOutOpBswap outop_revbit32 = { - .base.static_constraint = C_NotImplemented, + .base.static_constraint = C_O1_I1(r, r), + .out_rr = tgen_revbit32, }; +static void tgen_revbit64(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) +{ + tcg_out_insn(s, rr_sf, RBIT, TCG_TYPE_I64, a0, a1); +} + static const TCGOutOpUnary outop_revbit64 = { - .base.static_constraint = C_NotImplemented, + .base.static_constraint = C_O1_I1(r, r), + .out_rr = tgen_revbit64, }; static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) -- 2.43.0