Re: [PATCH 7/7] target/arm: Separate cpu types max-v8 and max-v9

On 8/6/26 09:39, Richard Henderson wrote:
> -    t = FIELD_DP64(t, ID_AA64ISAR2, CSSC, 2);     /* FEAT_CSSC, FEAT_CMPBR */
> +    t = FIELD_DP64(t, ID_AA64ISAR2, CSSC, 2);     /* v8.7: FEAT_CSSC */

This field should be 1 for CSSC without CMPBR.
I got this right the first time, but lost in a rebase/reorg.

> +    /* v9.0 prohibits FEAT_DoubleLock. */
> +    FIELD_DP64_IDREG(isar, ID_AA64DFR0, DOUBLELOCK, -1);
> +    isar->dbgdevid = FIELD_DP32(isar->dbgdevid, DBGDEVID, DOUBLELOCK, 0);

I missed adjusting ID_AA64PFR0.RAS.


r~