[PATCH v2 2/6] target/arm: Enable writes to SCR_EL3.TID{3,5}
Richard Henderson <[email protected]>
| Newsgroups | org.nongnu.qemu-arm,org.nongnu.qemu-devel |
|---|---|
| Message-ID | <[email protected]> |
Reviewed-by: Peter Maydell <[email protected]> Signed-off-by: Richard Henderson <[email protected]> --- target/arm/cpu-features.h | 5 +++++ target/arm/cpu.h | 2 ++ target/arm/helper.c | 3 +++ 3 files changed, 10 insertions(+) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index d6f8b4d065..f0b354445f 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -1402,6 +1402,11 @@ static inline bool isar_feature_aa64_idst(const ARMISARegisters *id) return FIELD_EX64_IDREG(id, ID_AA64MMFR2, IDS) != 0; } +static inline bool isar_feature_aa64_idte3(const ARMISARegisters *id) +{ + return FIELD_EX64_IDREG(id, ID_AA64MMFR2, IDS) >= 2; +} + static inline bool isar_feature_aa64_half_evt(const ARMISARegisters *id) { return FIELD_EX64_IDREG(id, ID_AA64MMFR2, EVT) >= 1; diff --git a/target/arm/cpu.h b/target/arm/cpu.h index a471b87aa5..41bfda65d4 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1786,6 +1786,8 @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) #define SCR_EASE (1ULL << 19) #define SCR_NMEA (1ULL << 20) #define SCR_FIEN (1ULL << 21) +#define SCR_TID3 (1ULL << 22) +#define SCR_TID5 (1ULL << 23) #define SCR_ENSCXT (1ULL << 25) #define SCR_ATA (1ULL << 26) #define SCR_FGTEN (1ULL << 27) diff --git a/target/arm/helper.c b/target/arm/helper.c index c88af981e2..8ab0075628 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -796,6 +796,9 @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) if (cpu_isar_feature(aa64_rng_trap, cpu)) { valid_mask |= SCR_TRNDR; } + if (cpu_isar_feature(aa64_idte3, cpu)) { + valid_mask |= SCR_TID5 | SCR_TID3; + } } else { valid_mask &= ~(SCR_RW | SCR_ST); if (cpu_isar_feature(aa32_ras, cpu)) { -- 2.43.0