[RFC PATCH 09/18] accel/tcg: Allow phost to be NULL in probe_access_flags

Do not require the caller to create a dummy variable.
The one instance so far is riscv check_zicbom_access.

Signed-off-by: Richard Henderson <[email protected]>
---
 include/accel/tcg/probe.h    | 3 ++-
 accel/tcg/cputlb.c           | 4 +++-
 accel/tcg/user-exec.c        | 5 ++++-
 target/riscv/tcg/op_helper.c | 3 +--
 4 files changed, 10 insertions(+), 5 deletions(-)

diff --git a/include/accel/tcg/probe.h b/include/accel/tcg/probe.h
index 06faf1269d..477320c88d 100644
--- a/include/accel/tcg/probe.h
+++ b/include/accel/tcg/probe.h
@@ -68,7 +68,8 @@ static inline void *probe_read(CPUArchState *env, vaddr addr, int size,
  *   - if @nonfault is false, raise an exception at @addr
  *   - otherwise return TLB_INVALID_MASK.
  *
- * Otherwise, return the TLB_FLAGS_MASK for the page, and set @phost:
+ * Otherwise, return the TLB_FLAGS_MASK for the page,
+ * and, if @phost is not NULL, set @phost:
  *   - host address for @addr, if direct host accesses are allowed,
  *   - otherwise NULL.
  *
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index a192c50e90..c2ea31a397 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -1465,6 +1465,7 @@ int probe_access_flags(CPUArchState *env, vaddr addr, vaddr first, vaddr last,
                        bool nonfault, void **phost, uintptr_t retaddr)
 {
     CPUTLBEntryFull *full;
+    void *discard_host;
     int flags;
 
     assert(first <= addr);
@@ -1473,7 +1474,8 @@ int probe_access_flags(CPUArchState *env, vaddr addr, vaddr first, vaddr last,
 
     flags = probe_access_internal(env_cpu(env), addr, last - addr + 1,
                                   access_type, mmu_idx, nonfault,
-                                  phost, &full, retaddr, true);
+                                  phost ? phost : &discard_host,
+                                  &full, retaddr, true);
 
     /* Handle clean RAM pages. */
     if (unlikely(flags & TLB_NOTDIRTY)) {
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index 44e9f7fa1a..3578282a3d 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -801,7 +801,10 @@ int probe_access_flags(CPUArchState *env, vaddr addr, vaddr first, vaddr last,
     assert(((first ^ last) & TARGET_PAGE_MASK) == 0);
 
     flags = probe_access_internal(env, addr, access_type, nonfault, ra);
-    *phost = (flags & TLB_INVALID_MASK) ? NULL : g2h_vaddr(env_cpu(env), addr);
+    if (phost) {
+        *phost = (flags & TLB_INVALID_MASK ? NULL
+                  : g2h_vaddr(env_cpu(env), addr));
+    }
     return flags;
 }
 
diff --git a/target/riscv/tcg/op_helper.c b/target/riscv/tcg/op_helper.c
index b18bf683f4..9c0cfd35fc 100644
--- a/target/riscv/tcg/op_helper.c
+++ b/target/riscv/tcg/op_helper.c
@@ -232,7 +232,6 @@ static void check_zicbom_access(CPURISCVState *env,
     RISCVCPU *cpu = env_archcpu(env);
     int mmu_idx = riscv_env_mmu_index(env, false);
     uint16_t cbomlen = cpu->cfg.cbom_blocksize;
-    void *phost;
     int ret;
 
     /* Mask off low-bits to align-down to the cache-block. */
@@ -251,7 +250,7 @@ static void check_zicbom_access(CPURISCVState *env,
      * permitted to access the cache block is UNSPECIFIED."
      */
     ret = probe_access_flags(env, address, address, address + cbomlen - 1,
-                             MMU_DATA_LOAD, mmu_idx, true, &phost, ra);
+                             MMU_DATA_LOAD, mmu_idx, true, NULL, ra);
     if (ret != TLB_INVALID_MASK) {
         /* Success: readable */
         return;
-- 
2.43.0