Re: [PATCH v2 10/10] target/arm: Separate cpu types max-v8 and max-v9

On 8/17/26 06:56, Peter Maydell wrote:
> On Wed, 12 Aug 2026 at 21:45, Richard Henderson
> <[email protected]> wrote:
>>
>> Do not include v9-only features in "max-v8".
>> Do not include the prohibited v8 features in "max-v9".
>> In tcg mode, define "max" as "max-v9".
>>
>> Signed-off-by: Richard Henderson <[email protected]>
> 
> 
> 
>> +/*
>> + * -cpu max-v9: an ARMv9 CPU with as many features enabled as
>> + * our emulation supports.
>> + */
>> +void aarch64_max_v9_tcg_initfn(Object *obj)
>> +{
>> +    ARMCPU *cpu = ARM_CPU(obj);
>> +    ARMISARegisters *isar = &cpu->isar;
>> +    uint64_t t;
>> +
>> +    /* Armv9.0 is based on a minimum of Armv8.5. */
>> +    aarch64_max_v8_tcg_initfn(obj);
>> +
>> +    /*
>> +     * Armv9.0 does not support AArch32 except at EL0,
>> +     * therefore indicate EL1 through EL3 are AArch64-only.
>> +     */
>> +    t = GET_IDREG(isar, ID_AA64PFR0);
>> +    t = FIELD_DP64(t, ID_AA64PFR0, EL1, 1);
>> +    t = FIELD_DP64(t, ID_AA64PFR0, EL2, 1);
>> +    t = FIELD_DP64(t, ID_AA64PFR0, EL3, 1);
>> +    SET_IDREG(isar, ID_AA64PFR0, t);
>> +
>> +    /* v9.0 prohibits FEAT_DoubleLock. */
>> +    FIELD_DP64_IDREG(isar, ID_AA64DFR0, DOUBLELOCK, -1);
>> +    FIELD_DP64_IDREG(isar, ID_AA64PFR0, RAS, 1);
> 
> Don't these two lines need to go inside the relevant
> GET_IDREG...SET_IDREG blocks ?

I thought it was clearer to do all the DoubleLock stuff separately.

>> +    isar->dbgdevid = FIELD_DP32(isar->dbgdevid, DBGDEVID, DOUBLELOCK, 0);
> 
> ...and this line is setting a field in DBGDEVID, which isn't
> accessible unless we have AArch32 EL1, which v9 doesn't.

True, but it's there and leaving it seems wrong.

Do we want to explicitly zero all the isar regs that are supposed to be missing?  I know a 
heap of them are still present, as the describe what is and is not available at EL0.

> Testing, I see that qemu-arm and qemu-system-arm don't have
> "max-v8" visible. I think they should.
Ok.


r~