Re: [PATCH v2 4/8] target/arm: Add new feature ARM_FEATURE_NEON_TRAPS

On 8/17/26 05:38, Peter Maydell wrote:
> The traps configurable via CPACR.ASEDIS and HCPTR.TASE that trap only
> Neon instructions are unfortunately IMPDEF about whether they are
> implemented or not, and there is no ID register field that identifies
> whether they are present.  In practice, they are present on every
> implementation I have checked except for the Cortex-A8 (which was the
> first CPU with Neon).
> 
> Add a new feature ARM_FEATURE_NEON_TRAPS which we set on every
> ARM_FEATURE_NEON CPU except the Cortex-A8, and make the CPACR.ASEDIS
> and HCPTR.TASE bits RAZ/WI unless the CPU has ARM_FEATURE_NEON and
> ARM_FEATURE_NEON_TRAPS.
> 
> Signed-off-by: Peter Maydell<[email protected]>
> ---
> We seem to be a little confused about whether ARM_FEATURE_NEON
> means "AArch32 Neon" or "AArch32 Neon or AArch64 ASIMD". I have
> not attempted to unpick that here. I have also not gone so far
> as to set NEON_TRAPS for the accelerator CPUs, since they won't
> be using the sysreg access functions anyway and (other than KVM)
> they don't support AArch32.
> ---
>   target/arm/cpu-max.c   |  1 +
>   target/arm/cpu.h       |  7 +++++++
>   target/arm/cpu64.c     |  1 +
>   target/arm/helper.c    | 17 +++++++++++++++--
>   target/arm/tcg/cpu32.c |  8 ++++++++
>   target/arm/tcg/cpu64.c | 10 ++++++++++
>   6 files changed, 42 insertions(+), 2 deletions(-)

Reviewed-by: Richard Henderson <[email protected]>

r~