Re: [PATCH] target/arm: Correct reset value of SCTLR for arm926

On 8/18/26 04:58, Peter Maydell wrote:
> For the arm926 CPU we reset the SCTLR to 0x00090078.  This is not the
> value specified in the ARM926EJ-S TRM (ARM DDI 0198E), which states
> that bits 16 and 18 are SBO, bit 17 is SBZ, and bits [31:19] are SBZ.
> It's also not the value seen on real hardware.
> 
> This has been wrong in QEMU since 2007 when we first started actively
> resetting the SCTLR to some fixed value rather than zero.
> 
> This wrong value didn't affect any of QEMU's behaviour, because we
> don't implement any handling of the old pre-v6 meanings of these bits
> (which were IMPDEF), and their v8 reuse is guarded by appropriate
> version checks.
> 
> Correct the reset value to 0x00050078 (i.e set bit 18 and not 19).
> 
> (We use the same reset value for the arm1020; this might also be
> wrong, but as the ARM1020 TRM doesn't seem to be available we can't
> check, so leave it as-is.)

Found ARM DDI 0244C, ARM1026EJ-S r0p2:

https://www.datasheetarchive.com/datasheet/ARM1026EJ-S/ARM?term=ARM1026EJ-S%25E2%2584%25A2&version=1

which appears to be what arm1026_initfn is modeling.

It also has [23:19] SBZ, [18] SBO, 17 [SBZ], 16 [SBO].

> 
> Cc: [email protected]
> Fixes: 610c3c8afd99f4f11 ("Reset ARM cp15.c1_sys to default values. Fix XScale cp15 accesses.")
> Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/4202
> Signed-off-by: Peter Maydell <[email protected]>
> ---
>   target/arm/tcg/cpu32.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)

Anyway, for this one,
Reviewed-by: Richard Henderson <[email protected]>


r~