Re: [RFC PATCH v7 04/18] arm/cpu: Add infra to handle generated ID register definitions

> On 26 Jul 2026, at 8:59 PM, Eric Auger <[email protected]> wrote:
> 
> !-------------------------------------------------------------------|
>  CAUTION: External Email
> 
> |-------------------------------------------------------------------!
> 
> Introduce an infrastructure to store the definition of all ID regs:
> This include their name, index and array of named fields.
> 
> Signed-off-by: Eric Auger <[email protected]>
> Signed-off-by: Cornelia Huck <[email protected]>
> Co-authored-by: Khushit Shah <[email protected]>
> 
> ---
> 
> v5 -> v6:
> - add ArmIdRegArchVal
> ---
> target/arm/cpu-idregs.h | 41 +++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 41 insertions(+)
> create mode 100644 target/arm/cpu-idregs.h
> 
> diff --git a/target/arm/cpu-idregs.h b/target/arm/cpu-idregs.h
> new file mode 100644
> index 0000000000..245f1c8103
> --- /dev/null
> +++ b/target/arm/cpu-idregs.h
> @@ -0,0 +1,41 @@
> +/*
> + * handle ID registers and their fields
> + *
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + */
> +#ifndef TARGET_ARM_CPU_IDREGS_H
> +#define TARGET_ARM_CPU_IDREGS_H
> +
> +#include "qemu/osdep.h"
> +#include "qemu/error-report.h"
> +#include "cpu.h"
> +#include "cpu-sysregs.h"
> +
> +typedef struct ArmIdRegArchVal {
> +    uint64_t value;
> +    const char *name;
I guess the name is not required, right?

> +} ArmIdRegArchVal;
> +
> +typedef struct ARM64SysRegField {
> +    const char *name; /* name of the field, for instance CTR_EL0_IDC */
> +    ARMIDRegisterIdx index; /* parent register, e.g. CTR_EL0_IDX */
> +    int shift; /* lsb of the field in the register */
> +    int length; /* highest bit number */
> +    ArmIdRegArchVal *arch_vals;
> +    uint32_t arch_vals_count;
> +} ARM64SysRegField;
> +
> +typedef struct ARM64SysReg {
> +    const char *name;   /* name of the sysreg, for instance CTR_EL0 */
> +    ARMIDRegisterIdx index; /* register index, e.g. CTR_EL0_IDX */
> +    struct ARM64SysRegField *fields;
> +    uint32_t fields_count;
> +    uint64_t writable_mask;
> +} ARM64SysReg;
> +
> +/*
> + * List of exposed ID regs (automatically populated from AARCHMRS Registers.json)
> + */
> +extern ARM64SysReg arm64_id_regs[NUM_ID_IDX];
> +
> +#endif
> -- 
> 2.53.0
>