Re: [RFC PATCH v7 03/18] target/arm/cpu-sysregs.h.inc: Update with automatic generation

> On 26 Jul 2026, at 8:59 PM, Eric Auger <[email protected]> wrote:
> 
> !-------------------------------------------------------------------|
>  CAUTION: External Email
> 
> |-------------------------------------------------------------------!
> 
> Generated definitions with scripts/update-aarch64-cpu-sysregs-header.py
> based on "AARCHMRS containing the JSON files for Arm A-profile
> architecture (2026-03)" Registers.json file.
> 
> Signed-off-by: Eric Auger <[email protected]>
> Signed-off-by: Cornelia Huck <[email protected]>
> Reviewed-by: Shameer Kolothum <[email protected]>
> ---
> target/arm/cpu-sysregs.h.inc | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
> 
> diff --git a/target/arm/cpu-sysregs.h.inc b/target/arm/cpu-sysregs.h.inc
> index ec5a12b0f4..2188cd7be0 100644
> --- a/target/arm/cpu-sysregs.h.inc
> +++ b/target/arm/cpu-sysregs.h.inc
> @@ -1,11 +1,20 @@
> /* SPDX-License-Identifier: GPL-2.0-or-later */
> +
> +/* This file is autogenerated by scripts/update-aarch64-cpu-sysregs-header.py */
> +/* DEF(<name>, <op0>, <op1>, <crn>, <crm>, <op2>) */
> +
> +DEF(AIDR_EL1, 3, 1, 0, 0, 7)
> +DEF(CCSIDR2_EL1, 3, 1, 0, 0, 2)
> +DEF(CCSIDR_EL1, 3, 1, 0, 0, 0)
As CCSIDR*_EL1 are demux registers, a single entry for them does
not make sense.

Warm Regards,
Khushit
> DEF(CLIDR_EL1, 3, 1, 0, 0, 1)
> DEF(CTR_EL0, 3, 3, 0, 0, 1)
> DEF(DCZID_EL0, 3, 3, 0, 0, 7)
> +DEF(GMID_EL1, 3, 1, 0, 0, 4)
> DEF(ID_AA64AFR0_EL1, 3, 0, 0, 5, 4)
> DEF(ID_AA64AFR1_EL1, 3, 0, 0, 5, 5)
> DEF(ID_AA64DFR0_EL1, 3, 0, 0, 5, 0)
> DEF(ID_AA64DFR1_EL1, 3, 0, 0, 5, 1)
> +DEF(ID_AA64DFR2_EL1, 3, 0, 0, 5, 2)
> DEF(ID_AA64FPFR0_EL1, 3, 0, 0, 4, 7)
> DEF(ID_AA64ISAR0_EL1, 3, 0, 0, 6, 0)
> DEF(ID_AA64ISAR1_EL1, 3, 0, 0, 6, 1)
> @@ -40,6 +49,10 @@ DEF(ID_MMFR5_EL1, 3, 0, 0, 3, 6)
> DEF(ID_PFR0_EL1, 3, 0, 0, 1, 0)
> DEF(ID_PFR1_EL1, 3, 0, 0, 1, 1)
> DEF(ID_PFR2_EL1, 3, 0, 0, 3, 4)
> +DEF(MIDR_EL1, 3, 0, 0, 0, 0)
> +DEF(MPIDR_EL1, 3, 0, 0, 0, 5)
> DEF(MVFR0_EL1, 3, 0, 0, 3, 0)
> DEF(MVFR1_EL1, 3, 0, 0, 3, 1)
> DEF(MVFR2_EL1, 3, 0, 0, 3, 2)
> +DEF(REVIDR_EL1, 3, 0, 0, 0, 6)
> +DEF(SMIDR_EL1, 3, 1, 0, 0, 6)
> -- 
> 2.53.0
>