Re: [PATCH v2 2/4] hw/arm/aspeed_ast2600: Introduce the ACRY SRAM

On 8/20/26 10:12, Jamin Lin wrote:
> Reuse the existing SRAM array convention on AspeedSoCState to add the
> 64 KiB ACRY SRAM region to the AST2600 at its real-silicon address
> (0x1e710000-0x1e71ffff).
> 
> Wrap the RAM in a container mapped at offset 0 so the ACRY engine wired
> up in a later patch can address the SRAM by relative offset without the
> device model knowing its mapping address.
> 
> Signed-off-by: Jamin Lin <[email protected]>
> ---
>   include/hw/arm/aspeed_soc.h |  1 +
>   hw/arm/aspeed_ast2600.c     | 17 +++++++++++++++++
>   2 files changed, 18 insertions(+)
> 
> diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
> index cd68c7f1ca..46e7854727 100644
> --- a/include/hw/arm/aspeed_soc.h
> +++ b/include/hw/arm/aspeed_soc.h
> @@ -69,6 +69,7 @@ struct AspeedSoCState {
>       MemoryRegion *dram_mr;
>       MemoryRegion dram_container;
>       MemoryRegion sram[ASPEED_SRAM_NUM];
> +    MemoryRegion sram_container[ASPEED_SRAM_NUM];
>       MemoryRegion spi_boot_container;
>       MemoryRegion spi_boot;
>       MemoryRegion vbootrom;
> diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
> index d1f18e471a..f23a51c8a4 100644
> --- a/hw/arm/aspeed_ast2600.c
> +++ b/hw/arm/aspeed_ast2600.c
> @@ -8,6 +8,7 @@
>    */
>   
>   #include "qemu/osdep.h"
> +#include "qemu/units.h"
>   #include "qapi/error.h"
>   #include "hw/misc/unimp.h"
>   #include "hw/arm/aspeed_soc.h"
> @@ -24,6 +25,7 @@
>   static const hwaddr aspeed_soc_ast2600_memmap[] = {
>       [ASPEED_DEV_SPI_BOOT]  = 0x00000000,
>       [ASPEED_DEV_SRAM0]     = 0x10000000,
> +    [ASPEED_DEV_SRAM1]     = 0x1E710000, /* ACRY SRAM */
>       [ASPEED_DEV_DPMCU]     = 0x18000000,
>       /* 0x16000000     0x17FFFFFF : AHB BUS do LPC Bus bridge */
>       [ASPEED_DEV_IOMEM]     = 0x1E600000,
> @@ -361,6 +363,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
>       AspeedSoCState *s = ASPEED_SOC(dev);
>       AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
>       qemu_irq irq;
> +    g_autofree char *sram1_name = NULL;
>       g_autofree char *sram_name = NULL;
>       int uart;
>   
> @@ -444,6 +447,19 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
>       memory_region_add_subregion(s->memory,
>                                   sc->memmap[ASPEED_DEV_SRAM0], &s->sram[0]);
>   
> +    /* ACRY SRAM */
> +    sram1_name = g_strdup_printf("aspeed.acry.sram.%d",
> +                                 CPU(&a->cpu[0])->cpu_index);
> +    if (!memory_region_init_ram(&s->sram[1], OBJECT(s), sram1_name,
> +                                sc->sram_size[1], errp)) {
> +        return;
> +    }
> +    memory_region_init(&s->sram_container[1], OBJECT(s),
> +                       "aspeed.acry.sram-container", sc->sram_size[1]);
> +    memory_region_add_subregion(&s->sram_container[1], 0, &s->sram[1]);
> +    memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SRAM1],
> +                                &s->sram_container[1]);
> +
>       /* DPMCU */
>       aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->dpmcu),
>                                     "aspeed.dpmcu",
> @@ -765,6 +781,7 @@ static void aspeed_soc_ast2600_class_init(ObjectClass *oc, const void *data)
>       sc->valid_cpu_types = valid_cpu_types;
>       sc->silicon_rev  = AST2600_A3_SILICON_REV;
>       sc->sram_size[0] = 0x16400;
> +    sc->sram_size[1] = 64 * KiB; /* ACRY SRAM */
>       sc->spis_num     = 2;
>       sc->ehcis_num    = 2;
>       sc->wdts_num     = 4;

Reviewed-by: Cédric Le Goater <[email protected]>

Thanks,

C.