Re: [PATCH v2] target/arm: Correct reset value of SCTLR for arm926, arm1026

On 8/21/26 04:41, Peter Maydell wrote:
> For the arm926 CPU we reset the SCTLR to 0x00090078.  This is not the
> value specified in the ARM926EJ-S TRM (ARM DDI 0198E), which states
> that bits 16 and 18 are SBO, bit 17 is SBZ, and bits [31:19] are SBZ.
> It's also not the value seen on real hardware.
> 
> Similarly, for the arm1026 we use the same SCTLR reset value but
> the TRM says that bits 18 and 16 are the SBO ones.
> 
> This has been wrong in QEMU since 2007 when we first started actively
> resetting the SCTLR to some fixed value rather than zero.
> 
> This wrong value didn't affect any of QEMU's behaviour, because we
> don't implement any handling of the old pre-v6 meanings of these bits
> (which were IMPDEF), and their v8 reuse is guarded by appropriate
> version checks.
> 
> Correct the reset values to 0x00050078 (i.e set bit 18 and not 19).
> 
> Cc:[email protected]
> Fixes: 610c3c8afd99f4f11 ("Reset ARM cp15.c1_sys to default values. Fix XScale cp15 accesses.")
> Resolves:https://gitlab.com/qemu-project/qemu/-/work_items/4202
> Signed-off-by: Peter Maydell<[email protected]>
> ---
> v2: fix arm1026 as well, since RTH found its TRM
> ---
>   target/arm/tcg/cpu32.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)

Reviewed-by: Richard Henderson <[email protected]>

r~