[PATCH v3 0/5] hw/riscv: Add K230 DWC SSI Standard PIO support

Hi,

This series adds a reusable Standard PIO model for the Synopsys DWC SSI
controller. The K230 machine has three such controllers, and the later
patches add their machine integration.

This series supersedes the previous V2 series:

  https://lore.kernel.org/qemu-devel/[email protected]/T/

The V2 series superseded the previous K230-specific SSI series:

  https://lore.kernel.org/qemu-devel/[email protected]/

The first patch adds the Standard SPI register subset, configurable FIFO
and chip-select resources, four transfer modes, reset and migration state,
and RAZ/WI handling for unsupported enhanced SPI, DMA, and XIP registers.
It uses the DWC CTRLR0 layout, where TMOD is at bits [11:10]. The second
patch adds the Standard PIO interrupt support. The remaining patches add
the K230 instances, PLIC routing, and an optional SPI NOR on spi0 CS0.

Changes since v2:

* Rename the controller model and integration from DesignWare/DW to DWC.
* Clarify the DWC CTRLR0.TMOD layout and keep DW APB SSI variants out of
  scope.
* Refine Standard PIO transfer pacing and FIFO handling for long transfers.

Enhanced SPI, internal IDMA, HI_SYS, and XIP remain separate follow-up
series. The older DW APB SSI TMOD encoding is not part of this series.

References:

K230 Technical Reference Manual:

  https://github.com/revyos/external-docs/blob/79b3a79072412ead81427e6755b4d9e6d9ded8d8/K230/en-us/K230_Technical_Reference_Manual_V0.3.1_20241118.pdf

Linux DWC SSI driver and binding:

  https://github.com/torvalds/linux/blob/f9a2394a23482bfd330911e9c8295b71724feacd/drivers/spi/spi-dw-core.c
  https://github.com/torvalds/linux/blob/f9a2394a23482bfd330911e9c8295b71724feacd/drivers/spi/spi-dw.h
  https://github.com/torvalds/linux/blob/f9a2394a23482bfd330911e9c8295b71724feacd/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml

Intel Arria 10 HPS TRM, used only for comparison with the DW APB SSI
layout:

  https://www.intel.com/content/www/us/en/docs/programmable/683711/21-2/hard-processor-system-technical-reference.html

Testing:

* Built qemu-system-riscv64 and the K230 DWC SSI qtest target.
* Ran all 14 K230 DWC SSI qtests, including Standard PIO modes, register
  contracts, interrupts and PLIC routing, and Standard SPI NOR reads.
* Standard 1-1-1 transfers were also exercised manually through the K230
  SDK U-Boot and Linux SPI paths against the attached flash.
* git diff --check passed.
* checkpatch.pl reported no code errors; its MAINTAINERS coverage warnings
  are expected because this series does not modify MAINTAINERS.

Suggested-by: Bin Meng <[email protected]>
Suggested-by: Chao Liu <[email protected]>
Suggested-by: Anirudh Srinivasan <[email protected]>

Kangjie Huang (5):
  hw/ssi: Add Synopsys DWC SSI standard PIO controller
  hw/ssi: Add DWC SSI standard interrupt support
  hw/riscv/k230: Instantiate DWC SSI controllers
  hw/riscv/k230: Route SSI interrupts to the PLIC
  hw/riscv/k230: Attach a standard SPI NOR flash

 docs/system/riscv/k230.rst      |    2 +
 hw/riscv/Kconfig                |    2 +
 hw/riscv/k230.c                 |  178 ++++-
 hw/ssi/Kconfig                  |    4 +
 hw/ssi/dwc_ssi.c                | 1103 +++++++++++++++++++++++++++++++
 hw/ssi/meson.build              |    1 +
 include/hw/riscv/k230.h         |    7 +
 include/hw/ssi/dwc_ssi.h        |   79 +++
 tests/qtest/k230-dwc-ssi-test.c |  702 ++++++++++++++++++++
 tests/qtest/meson.build         |    4 +-
 10 files changed, 2066 insertions(+), 16 deletions(-)
 create mode 100644 hw/ssi/dwc_ssi.c
 create mode 100644 include/hw/ssi/dwc_ssi.h
 create mode 100644 tests/qtest/k230-dwc-ssi-test.c


base-commit: b428fe036233cbd15d37e3c027ab6ca4d3661a80
-- 
2.43.0