Re: [PATCH 03/56] disas/riscv: Use signed type for vector immediates

Philippe Mathieu-Daudé <[email protected]>
Newsgroups org.nongnu.qemu-devel,org.nongnu.qemu-riscv
Message-ID <[email protected]>
On 10/8/26 00:34, Richard Henderson wrote:
> From: TANG Tiancheng <[email protected]>
> 
> operand_vimm() sign-extends the 5-bit vector immediate field in bits
> 19:15, but returns uint32_t. This sends negative immediates through an
> unsigned type before they are assigned to rv_decode.imm.
> 
> Return int32_t to match the signed value extracted by the helper.
> 
> Signed-off-by: TANG Tiancheng <[email protected]>
> Reviewed-by: LIU Zhiwei <[email protected]>

(Missing your S-o-b)

Reviewed-by: Philippe Mathieu-Daudé <[email protected]>

> Message-Id: <20260703-b4-disas-xthead-fix-riscv-next-v4-3-84c566330bc7@linux.alibaba.com>
> ---
>   disas/riscv.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
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