Re: [PATCH v2 1/2] riscv: csr: do not drop C bit on misa write

On Mon, Aug 17, 2026 at 06:06:37PM +0800, Vladimir Isaev wrote:
> According to spec:
> > Writing misa may increase IALIGN, e.g., by disabling the "C" extension.
> > If an instruction that would write misa increases IALIGN, and the
> > subsequent instruction’s address is not IALIGN-bit aligned, the
> > write to misa is suppressed, leaving misa unchanged.
> 
> So attempt to disable C extension if next instruction is not aligned should not
> change the misa.
> 
> Reviewed-by: Alistair Francis <[email protected]>
> Signed-off-by: Vladimir Isaev <[email protected]>
Reviewed-by: Chao Liu <[email protected]>

Thanks,
Chao

> ---
>  target/riscv/tcg/csr.c | 10 +++++++---
>  1 file changed, 7 insertions(+), 3 deletions(-)
> 
> diff --git a/target/riscv/tcg/csr.c b/target/riscv/tcg/csr.c
> index 36f2004bc5..dbfb3381ef 100644
> --- a/target/riscv/tcg/csr.c
> +++ b/target/riscv/tcg/csr.c
> @@ -2182,9 +2182,13 @@ static RISCVException write_misa(CPURISCVState *env, int csrno,
>      /* Mask extensions that are not supported by this hart */
>      val &= env->misa_ext_mask;
>  
> -    /* Suppress 'C' if next instruction is not aligned. */
> -    if ((val & RVC) && (get_next_pc(env, ra) & 3) != 0) {
> -        val &= ~RVC;
> +    /* drop write if RVC is cleared and next instruction is not aligned */
> +    if ((env->misa_ext & RVC) && !(val & RVC) &&
> +         (get_next_pc(env, ra) & 3) != 0) {
> +        qemu_log_mask(LOG_GUEST_ERROR, "Unable to write MISA ext value "
> +                      "0x%x, MISA.C disable failed\n", env->misa_ext);
> +
> +        return RISCV_EXCP_NONE;
>      }
>  
>      /* Disable RVG if any of its dependencies are disabled */
> -- 
> 2.55.0
>