[PATCH for-11.1 13/17] target/riscv/debug: Fix migration post_load icount_enabled() test
Daniel Henrique Barboza <[email protected]>
| Newsgroups | org.nongnu.qemu-riscv,org.nongnu.qemu-devel |
|---|---|
| Message-ID | <[email protected]> |
From: Nicholas Piggin <[email protected]> itrigger_enabled is relevant to the !icount_enabled() path, the test in debug_post_load() is inverted. While we're at it, move debug CPU post_load details into debug.c since there's no need for machine.c to know internals of how debug.c maintains debug state. Fixes: 577f028694 ("target/riscv: Add itrigger_enabled field to CPURISCVState") Signed-off-by: Nicholas Piggin <[email protected]> Reviewed-by: Daniel Henrique Barboza <[email protected]> --- target/riscv/machine.c | 13 ++++++++----- target/riscv/tcg/debug.c | 9 ++++++++- target/riscv/tcg/debug.h | 2 +- 3 files changed, 17 insertions(+), 7 deletions(-) diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 0ab613a298..82d2e11eb3 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -228,18 +228,21 @@ static bool debug_needed(void *opaque) { RISCVCPU *cpu = opaque; - return cpu->cfg.debug; + if (kvm_enabled()) { + return false; + } + + return tcg_enabled() && cpu->cfg.debug; } static int debug_post_load(void *opaque, int version_id) { +#ifdef CONFIG_TCG RISCVCPU *cpu = opaque; CPURISCVState *env = &cpu->env; - if (icount_enabled()) { - env->itrigger_enabled = riscv_itrigger_enabled(env); - } - + riscv_cpu_debug_post_load(env); +#endif return 0; } diff --git a/target/riscv/tcg/debug.c b/target/riscv/tcg/debug.c index 6cdf89c638..56f9ceb042 100644 --- a/target/riscv/tcg/debug.c +++ b/target/riscv/tcg/debug.c @@ -675,7 +675,7 @@ static bool check_itrigger_priv(CPURISCVState *env, int index) return icount_priv_match(env, index); } -bool riscv_itrigger_enabled(CPURISCVState *env) +static bool riscv_itrigger_enabled(CPURISCVState *env) { int count; @@ -1155,6 +1155,13 @@ void riscv_cpu_debug_change_priv(CPURISCVState *env) } } +void riscv_cpu_debug_post_load(CPURISCVState *env) +{ + if (!icount_enabled()) { + env->itrigger_enabled = riscv_itrigger_enabled(env); + } +} + void riscv_trigger_reset_hold(CPURISCVState *env) { target_ulong tdata1 = build_tdata1(env, TRIGGER_TYPE_AD_MATCH, 0, 0); diff --git a/target/riscv/tcg/debug.h b/target/riscv/tcg/debug.h index 88d34ecac9..6246bedff3 100644 --- a/target/riscv/tcg/debug.h +++ b/target/riscv/tcg/debug.h @@ -151,9 +151,9 @@ void riscv_trigger_realize(CPURISCVState *env); void riscv_trigger_unrealize(CPURISCVState *env); void riscv_trigger_reset_hold(CPURISCVState *env); -bool riscv_itrigger_enabled(CPURISCVState *env); void riscv_itrigger_update_priv(CPURISCVState *env); void riscv_cpu_debug_change_priv(CPURISCVState *env); +void riscv_cpu_debug_post_load(CPURISCVState *env); #endif /* RISCV_DEBUG_H */ -- 2.43.0