[PATCH v2 08/18] target/riscv: Add packed SIMD horizontal reduction instructions
Molly Chen <[email protected]>
| Newsgroups | org.nongnu.qemu-riscv,org.nongnu.qemu-devel |
|---|---|
| Message-ID | <ccd16153de572b5980cd19949160d87ab26fef9b.1784280142.git.xiaoou@iscas.ac.cn> |
Signed-off-by: Molly Chen <[email protected]> --- target/riscv/helper.h | 8 ++++++++ target/riscv/insn32.decode | 8 ++++++++ target/riscv/tcg/insn_trans/trans_rvp.c.inc | 8 ++++++++ target/riscv/tcg/psimd_helper.c | 15 +++++++++++++++ 4 files changed, 39 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index d0b13cf3c6a..5fe650c5d71 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1512,3 +1512,11 @@ DEF_HELPER_3(psas_wx, i64, env, i64, i64) DEF_HELPER_3(pssa_wx, i64, env, i64, i64) DEF_HELPER_3(paas_wx, i64, env, i64, i64) DEF_HELPER_3(pasa_wx, i64, env, i64, i64) + +/* Packed SIMD - Horizontal Reduction Operations */ +DEF_HELPER_3(predsum_bs, tl, env, tl, tl) +DEF_HELPER_3(predsumu_bs, tl, env, tl, tl) +DEF_HELPER_3(predsum_hs, tl, env, tl, tl) +DEF_HELPER_3(predsumu_hs, tl, env, tl, tl) +DEF_HELPER_3(predsum_ws, i64, env, i64, i64) +DEF_HELPER_3(predsumu_ws, i64, env, i64, i64) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index e331ba6a38c..9d0f5c48b6d 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -1288,3 +1288,11 @@ psas_wx 1001001 ..... ..... 110 ..... 0111011 @r pssa_wx 1001011 ..... ..... 110 ..... 0111011 @r paas_wx 1001101 ..... ..... 110 ..... 0111011 @r pasa_wx 1001111 ..... ..... 110 ..... 0111011 @r + +# Packed SIMD - Horizontal Reduction Operations +predsum_bs 1001110 ..... ..... 100 ..... 0011011 @r +predsumu_bs 1011110 ..... ..... 100 ..... 0011011 @r +predsum_hs 1001100 ..... ..... 100 ..... 0011011 @r +predsumu_hs 1011100 ..... ..... 100 ..... 0011011 @r +predsum_ws 1001101 ..... ..... 100 ..... 0011011 @r +predsumu_ws 1011101 ..... ..... 100 ..... 0011011 @r diff --git a/target/riscv/tcg/insn_trans/trans_rvp.c.inc b/target/riscv/tcg/insn_trans/trans_rvp.c.inc index 61e1fb8d816..9f2ae9da1d1 100644 --- a/target/riscv/tcg/insn_trans/trans_rvp.c.inc +++ b/target/riscv/tcg/insn_trans/trans_rvp.c.inc @@ -658,3 +658,11 @@ GEN_SIMD_TRANS_64_VXSAT(pssa_wx) GEN_SIMD_TRANS_64(paas_wx) GEN_SIMD_TRANS_64(pasa_wx) +/* Packed SIMD - Horizontal Reduction Operations */ +GEN_SIMD_TRANS(predsum_bs) +GEN_SIMD_TRANS(predsumu_bs) +GEN_SIMD_TRANS(predsum_hs) +GEN_SIMD_TRANS(predsumu_hs) +GEN_SIMD_TRANS_64(predsum_ws) +GEN_SIMD_TRANS_64(predsumu_ws) + diff --git a/target/riscv/tcg/psimd_helper.c b/target/riscv/tcg/psimd_helper.c index ccc43b2dda0..0acf0414bf9 100644 --- a/target/riscv/tcg/psimd_helper.c +++ b/target/riscv/tcg/psimd_helper.c @@ -2096,3 +2096,18 @@ GEN_PSIMD_XPAIR_AVG_BINOP(pasa_wx, uint64_t, int32_t, int64_t, EXTRACT32, INSERT32, ELEMS_W, PSIMD_DO_ADD, PSIMD_DO_SUB) +/* Horizontal sum operations */ + +GEN_PSIMD_REDSUM(predsum_bs, target_ulong, int64_t, int8_t, + EXTRACT8, ELEMS_B, (int64_t)(int32_t)rs2) +GEN_PSIMD_REDSUM(predsumu_bs, target_ulong, uint64_t, uint8_t, + EXTRACT8, ELEMS_B, rs2) +GEN_PSIMD_REDSUM(predsum_hs, target_ulong, int64_t, int16_t, + EXTRACT16, ELEMS_H, (int64_t)(int32_t)rs2) +GEN_PSIMD_REDSUM(predsumu_hs, target_ulong, uint64_t, uint16_t, + EXTRACT16, ELEMS_H, rs2) +GEN_PSIMD_REDSUM(predsum_ws, uint64_t, int64_t, int32_t, + EXTRACT32, ELEMS_W, (int64_t)rs2) +GEN_PSIMD_REDSUM(predsumu_ws, uint64_t, uint64_t, uint32_t, + EXTRACT32, ELEMS_W, rs2) + -- 2.34.1