[RFC PATCH 2/3] hw/riscv/k230: integrate SRAM device into SoC

Jian Cai <[email protected]> Mon, 20 Jul 2026 15:45:44 +0800
Newsgroups org.nongnu.qemu-riscv,org.nongnu.qemu-devel
Message-ID <[email protected]>
Replace the bare memory_region_init_ram() in k230_soc_realize()
with a proper SysBusDevice.  Wire up object_initialize_child()
in k230_soc_init(), call sysbus_realize() and sysbus_mmio_map()
in k230_soc_realize(), and add the Kconfig + meson.build entries.

Update docs/system/riscv/k230.rst.

Signed-off-by: Jian Cai <[email protected]>
---
 docs/system/riscv/k230.rst | 8 ++++++++
 hw/riscv/Kconfig           | 4 ++++
 hw/riscv/k230.c            | 9 +++++----
 hw/riscv/meson.build       | 1 +
 include/hw/riscv/k230.h    | 3 ++-
 5 files changed, 20 insertions(+), 5 deletions(-)

diff --git a/docs/system/riscv/k230.rst b/docs/system/riscv/k230.rst
index cea8202e55..a7668fa065 100644
--- a/docs/system/riscv/k230.rst
+++ b/docs/system/riscv/k230.rst
@@ -111,3 +111,11 @@ this machine does not emulate those controllers yet. Replace ``${INITRD_END}``
 with the host-calculated value above when typing the command. ``cma=0`` avoids
 the SDK kernel reserving too much of the little-core memory window for initramfs
 boot.
+
+SRAM
+~~~~
+
+The K230 shared SRAM is a 2 MB on-chip RAM block at ``0x80200000``.  It has no
+software-visible controller registers -- the region is accessed directly via the
+AXI bus.  Clock gating and reset control are handled by separate
+system-controller peripherals (CMU and RMU).
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index de37c08cae..ee48ea530d 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -142,6 +142,9 @@ config XIANGSHAN_KUNMINGHU
     select RISCV_IMSIC
     select SERIAL_MM
 
+config K230_SRAM
+    bool
+
 config MIPS_BOSTON_AIA
     bool
     default y
@@ -161,4 +164,5 @@ config K230
     select RISCV_IMSIC
     select SERIAL_MM
     select UNIMP
+    select K230_SRAM
     select K230_WDT
diff --git a/hw/riscv/k230.c b/hw/riscv/k230.c
index 656f28190c..3469a9d43b 100644
--- a/hw/riscv/k230.c
+++ b/hw/riscv/k230.c
@@ -110,6 +110,7 @@ static void k230_soc_init(Object *obj)
     object_initialize_child(obj, "c908-cpu", cpu0, TYPE_RISCV_HART_ARRAY);
     object_initialize_child(obj, "k230-wdt0", &s->wdt[0], TYPE_K230_WDT);
     object_initialize_child(obj, "k230-wdt1", &s->wdt[1], TYPE_K230_WDT);
+    object_initialize_child(obj, "k230-sram", &s->sram, TYPE_K230_SRAM);
 
     qdev_prop_set_uint32(DEVICE(cpu0), "hartid-base", 0);
     qdev_prop_set_string(DEVICE(cpu0), "cpu-type", TYPE_RISCV_CPU_THEAD_C908);
@@ -162,10 +163,10 @@ static void k230_soc_realize(DeviceState *dev, Error **errp)
     c908_cpus = s->c908_cpu.num_harts;
 
     /* SRAM */
-    memory_region_init_ram(&s->sram, OBJECT(dev), "sram",
-                           memmap[K230_DEV_SRAM].size, &error_fatal);
-    memory_region_add_subregion(sys_mem, memmap[K230_DEV_SRAM].base,
-                                &s->sram);
+    if (!sysbus_realize(SYS_BUS_DEVICE(&s->sram), errp)) {
+        return;
+    }
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->sram), 0, memmap[K230_DEV_SRAM].base);
 
     /* BootROM */
     memory_region_init_rom(&s->bootrom, OBJECT(dev), "bootrom",
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
index 0d82ceacc4..80b7455141 100644
--- a/hw/riscv/meson.build
+++ b/hw/riscv/meson.build
@@ -20,5 +20,6 @@ riscv_ss.add(when: 'CONFIG_XIANGSHAN_KUNMINGHU', if_true: files('xiangshan_kmh.c
 riscv_ss.add(when: 'CONFIG_RISCV_MIPS_CPS', if_true: files('cps.c'))
 riscv_ss.add(when: 'CONFIG_MIPS_BOSTON_AIA', if_true: files('boston-aia.c'))
 riscv_ss.add(when: 'CONFIG_K230', if_true: files('k230.c'))
+riscv_ss.add(when: 'CONFIG_K230_SRAM', if_true: files('k230_sram.c'))
 
 hw_arch += {'riscv': riscv_ss}
diff --git a/include/hw/riscv/k230.h b/include/hw/riscv/k230.h
index 592e1c26bf..9f7baa513c 100644
--- a/include/hw/riscv/k230.h
+++ b/include/hw/riscv/k230.h
@@ -18,6 +18,7 @@
 #include "hw/core/boards.h"
 #include "hw/riscv/riscv_hart.h"
 #include "hw/watchdog/k230_wdt.h"
+#include "hw/riscv/k230_sram.h"
 
 #define C908_CPU_HARTID   (0)
 
@@ -33,7 +34,7 @@ typedef struct K230SoCState {
     RISCVHartArrayState c908_cpu; /* Small core */
 
     K230WdtState wdt[2];
-    MemoryRegion sram;
+    K230SramState sram;
     MemoryRegion bootrom;
 
     DeviceState *c908_plic;
-- 
2.43.0