[PATCH 20/26] hw/riscv: pfsoc: Correct PolarFire SoC DDR aliases
Bin Meng <[email protected]> Thu, 23 Jul 2026 23:18:47 +0800
| Newsgroups | org.nongnu.qemu-riscv,org.nongnu.qemu-devel |
|---|---|
| Message-ID | <[email protected]> |
The 64-bit cached and non-cached windows alias the complete physical DDR from offset zero. Treating them as only the portion above 1 GiB leaves valid Icicle Kit memory nodes unbacked with the board's 2 GiB. Map both high windows over the full machine RAM. Signed-off-by: Bin Meng <[email protected]> --- hw/riscv/microchip_pfsoc.c | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index f348de6fd4..a2fbc89222 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -570,15 +570,27 @@ static void microchip_icicle_kit_machine_init(MachineState *machine) TYPE_MICROCHIP_PFSOC); qdev_realize(DEVICE(&s->soc), NULL, &error_fatal); - /* Split RAM into low and high regions using aliases to machine->ram */ + /* + * The four CPU-visible windows alias the same physical DDR from offset + * zero. For the Icicle Kit's 2 GiB of DDR, they map as follows: + * + * CPU address Attribute Visible size DDR range + * 0x0080000000 32-bit cached 1 GiB [0, 1 GiB) + * 0x00c0000000 32-bit non-cached 1 GiB [0, 1 GiB) + * 0x1000000000 64-bit cached 2 GiB [0, 2 GiB) + * 0x1400000000 64-bit non-cached 2 GiB [0, 2 GiB) + * + * "Low" and "high" describe the CPU address windows, not the lower and + * upper portions of physical DDR. + */ mem_low_size = memmap[MICROCHIP_PFSOC_DRAM_LO].size; - mem_high_size = machine->ram_size - mem_low_size; + mem_high_size = machine->ram_size; memory_region_init_alias(mem_low, NULL, "microchip.icicle.kit.ram_low", machine->ram, 0, mem_low_size); memory_region_init_alias(mem_high, NULL, "microchip.icicle.kit.ram_high", machine->ram, - mem_low_size, mem_high_size); + 0, mem_high_size); /* Register RAM */ memory_region_add_subregion(system_memory, -- 2.34.1