Re: [PATCH 02/26] hw/riscv: pfsoc: Map the L2 zero device window

On Thu, Jul 23, 2026 at 11:18:29PM +0800, Bin Meng wrote:
> HSS uses a window at 0x0a000000 while setting up the L2 cache,
> decompressing its runtime image, and executing that image.
> The missing mapping causes the E51 to trap before firmware can
> initialize its UART.
> 
> Represent the window with RAM to provide its persistent read,
> write, and execute effects without claiming to model the L2
> cache itself.
> 
> Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Chao Liu <[email protected]>

Thanks,
Chao

> ---
> 
>  include/hw/riscv/microchip_pfsoc.h |  1 +
>  hw/riscv/microchip_pfsoc.c         | 13 +++++++++++++
>  2 files changed, 14 insertions(+)
> 
> diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
> index a30b944afa..612fd2b69c 100644
> --- a/include/hw/riscv/microchip_pfsoc.h
> +++ b/include/hw/riscv/microchip_pfsoc.h
> @@ -90,6 +90,7 @@ enum {
>      MICROCHIP_PFSOC_L2CC,
>      MICROCHIP_PFSOC_DMA,
>      MICROCHIP_PFSOC_L2LIM,
> +    MICROCHIP_PFSOC_L2ZERO,
>      MICROCHIP_PFSOC_PLIC,
>      MICROCHIP_PFSOC_MMUART0,
>      MICROCHIP_PFSOC_WDOG0,
> diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
> index 218cccab69..fd28ee75fe 100644
> --- a/hw/riscv/microchip_pfsoc.c
> +++ b/hw/riscv/microchip_pfsoc.c
> @@ -97,6 +97,7 @@ static const MemMapEntry microchip_pfsoc_memmap[] = {
>      [MICROCHIP_PFSOC_L2CC] =            {  0x2010000,       0x1000 },
>      [MICROCHIP_PFSOC_DMA] =             {  0x3000000,     0x100000 },
>      [MICROCHIP_PFSOC_L2LIM] =           {  0x8000000,     0x200000 },
> +    [MICROCHIP_PFSOC_L2ZERO] =          {  0xa000000,     0x200000 },
>      [MICROCHIP_PFSOC_PLIC] =            {  0xc000000,    0x4000000 },
>      [MICROCHIP_PFSOC_MMUART0] =         { 0x20000000,       0x1000 },
>      [MICROCHIP_PFSOC_WDOG0] =           { 0x20001000,       0x1000 },
> @@ -201,6 +202,7 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
>      MemoryRegion *rsvd0_mem = g_new(MemoryRegion, 1);
>      MemoryRegion *e51_dtim_mem = g_new(MemoryRegion, 1);
>      MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1);
> +    MemoryRegion *l2zero_mem = g_new(MemoryRegion, 1);
>      MemoryRegion *envm_data = g_new(MemoryRegion, 1);
>      MemoryRegion *qspi_xip_mem = g_new(MemoryRegion, 1);
>      char *plic_hart_config;
> @@ -277,6 +279,17 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
>                                  memmap[MICROCHIP_PFSOC_L2LIM].base,
>                                  l2lim_mem);
>  
> +    /*
> +     * HSS decompresses into the L2 zero-device window and executes there.
> +     * Model it as RAM because QEMU does not model the backing L2 cache.
> +     */
> +    memory_region_init_ram(l2zero_mem, NULL, "microchip.pfsoc.l2zero",
> +                           memmap[MICROCHIP_PFSOC_L2ZERO].size,
> +                           &error_fatal);
> +    memory_region_add_subregion(system_memory,
> +                                memmap[MICROCHIP_PFSOC_L2ZERO].base,
> +                                l2zero_mem);
> +
>      /* create PLIC hart topology configuration string */
>      plic_hart_config = riscv_plic_hart_config_string(ms->smp.cpus);
>  
> -- 
> 2.34.1
>