[PATCH v7 1/8] target/riscv: Add Zicclsm CPU option
| Newsgroups | org.nongnu.qemu-riscv,org.nongnu.qemu-devel |
|---|---|
| Message-ID | <[email protected]> |
From: Frank Chang <[email protected]> Add Zicclsm CPU option so that user can turn on/off misaligned loads and stores support. Signed-off-by: Frank Chang <[email protected]> Reviewed-by: Max Chou <[email protected]> Reviewed-by: Alistair Francis <[email protected]> --- target/riscv/cpu_cfg_fields.h.inc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_fields.h.inc index 9eb47af0a76..f8c27a574f8 100644 --- a/target/riscv/cpu_cfg_fields.h.inc +++ b/target/riscv/cpu_cfg_fields.h.inc @@ -139,6 +139,8 @@ BOOL_FIELD(has_priv_1_11) /* Always enabled for TCG if has_priv_1_11 */ BOOL_FIELD(ext_ziccrse) +BOOL_FIELD(ext_zicclsm) + /* Vendor-specific custom extensions */ BOOL_FIELD(ext_xtheadba) BOOL_FIELD(ext_xtheadbb) -- 2.43.0