Re: [PATCH v7 2/8] target/riscv: Enable Zicclsm for the compatible CPUs

On 8/5/2026 1:43 PM, [email protected] wrote:
> From: Frank Chang <[email protected]>
> 
> To support Zicclsm, let's enable Zicclsm for the following compatible
> CPUs:
> 
> - Base 32 CPU (to be backward compatible)
> - Base 64 CPU (to be backward compatible)
> - XuanTie (T-Head) C908
> - Tenstorrent Ascalon
> - Ventana Veyron V1
> - XiangShan Kunminghu
> - MIPS P8700 (ISA doesn't include Zicclsm, but their datasheet claims that
>    it has unaligned load/store support in hardware)
> 
> Signed-off-by: Frank Chang <[email protected]>
> Acked-by: Alistair Francis <[email protected]>


Reviewed-by: Daniel Henrique Barboza <[email protected]>

> ---
>   target/riscv/cpu.c | 7 +++++++
>   1 file changed, 7 insertions(+)
> 
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 5a82e6563bf..7ee89f6fc4b 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -3268,6 +3268,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
>           .cfg.ext_zicbom = true,
>           .cfg.ext_zicbop = true,
>           .cfg.ext_zicboz = true,
> +        .cfg.ext_zicclsm = true,
>           .cfg.ext_zicntr = true,
>           .cfg.ext_zicsr = true,
>           .cfg.ext_zifencei = true,
> @@ -3340,6 +3341,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
>           .cfg.ext_zicbom = true,
>           .cfg.ext_zicbop = true,
>           .cfg.ext_zicboz = true,
> +        .cfg.ext_zicclsm = true,
>           .cfg.ext_zicntr = true,
>           .cfg.ext_zicsr = true,
>           .cfg.ext_zifencei = true,
> @@ -3426,6 +3428,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
>           .cfg.ext_zbs = true,
>           .cfg.ext_zkt = true,
>           .cfg.ext_zbkc = true,
> +        .cfg.ext_zicclsm = true,
>           .cfg.ext_zicsr = true,
>           .cfg.ext_zifencei = true,
>           .cfg.ext_zihintpause = true,
> @@ -3469,6 +3472,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
>           .cfg.ext_zicbom = true,
>           .cfg.ext_zicbop = true,
>           .cfg.ext_zicboz = true,
> +        .cfg.ext_zicclsm = true,
>           .cfg.ext_zicntr = true,
>           .cfg.ext_zicond = true,
>           .cfg.ext_zicsr = true,
> @@ -3518,6 +3522,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
>   
>           /* ISA extensions */
>           .cfg.mmu = true,
> +        .cfg.ext_zicclsm = true,
>           .cfg.ext_zifencei = true,
>           .cfg.ext_zicsr = true,
>           .cfg.pmp = true,
> @@ -3577,6 +3582,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
>        * The RISC-V Instruction Set Manual: Volume I
>        * Unprivileged Architecture
>        */
> +    .cfg.ext_zicclsm = true,
>       .cfg.ext_zicntr = true,
>       .cfg.ext_zihpm = true,
>       .cfg.ext_zihintntl = true,
> @@ -3633,6 +3639,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
>           .misa_ext = RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU,
>           .priv_spec = PRIV_VERSION_1_12_0,
>           .cfg.max_satp_mode = VM_1_10_SV48,
> +        .cfg.ext_zicclsm = true,
>           .cfg.ext_zifencei = true,
>           .cfg.ext_zicsr = true,
>           .cfg.mmu = true,