Re: [PATCH v7 5/8] target/riscv: Support raising misaligned exceptions for floating-point loads/stores

On 8/5/2026 1:43 PM, [email protected] wrote:
> From: Frank Chang <[email protected]>
> 
> When the Zicclsm extension is not enabled, raise misaligned load/store
> exceptions for misaligned accesses from floating-point load/store
> instructions (RVF, RVD, Zfh).
> 
> Signed-off-by: Frank Chang <[email protected]>
> ---

Reviewed-by: Daniel Henrique Barboza <[email protected]>

>   target/riscv/tcg/insn_trans/trans_rvd.c.inc   | 6 ++++++
>   target/riscv/tcg/insn_trans/trans_rvf.c.inc   | 6 ++++++
>   target/riscv/tcg/insn_trans/trans_rvzfh.c.inc | 6 ++++++
>   3 files changed, 18 insertions(+)
> 
> diff --git a/target/riscv/tcg/insn_trans/trans_rvd.c.inc b/target/riscv/tcg/insn_trans/trans_rvd.c.inc
> index 3b9a745520a..1be2bee9465 100644
> --- a/target/riscv/tcg/insn_trans/trans_rvd.c.inc
> +++ b/target/riscv/tcg/insn_trans/trans_rvd.c.inc
> @@ -61,6 +61,9 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a)
>           memop |= MO_ATOM_IFALIGN;
>       }
>       memop |= ctx->mo_endianness;
> +    if (!ctx->cfg_ptr->ext_zicclsm) {
> +        memop |= MO_ALIGN;
> +    }
>   
>       decode_save_opc(ctx, 0);
>       addr = get_address(ctx, a->rs1, a->imm);
> @@ -86,6 +89,9 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a)
>           memop |= MO_ATOM_IFALIGN;
>       }
>       memop |= ctx->mo_endianness;
> +    if (!ctx->cfg_ptr->ext_zicclsm) {
> +        memop |= MO_ALIGN;
> +    }
>   
>       decode_save_opc(ctx, 0);
>       addr = get_address(ctx, a->rs1, a->imm);
> diff --git a/target/riscv/tcg/insn_trans/trans_rvf.c.inc b/target/riscv/tcg/insn_trans/trans_rvf.c.inc
> index e935523c93c..481f7282da7 100644
> --- a/target/riscv/tcg/insn_trans/trans_rvf.c.inc
> +++ b/target/riscv/tcg/insn_trans/trans_rvf.c.inc
> @@ -52,6 +52,9 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a)
>       if (ctx->cfg_ptr->ext_zama16b) {
>           memop |= MO_ATOM_WITHIN16;
>       }
> +    if (!ctx->cfg_ptr->ext_zicclsm) {
> +        memop |= MO_ALIGN;
> +    }
>   
>       decode_save_opc(ctx, 0);
>       addr = get_address(ctx, a->rs1, a->imm);
> @@ -75,6 +78,9 @@ static bool trans_fsw(DisasContext *ctx, arg_fsw *a)
>       if (ctx->cfg_ptr->ext_zama16b) {
>           memop |= MO_ATOM_WITHIN16;
>       }
> +    if (!ctx->cfg_ptr->ext_zicclsm) {
> +        memop |= MO_ALIGN;
> +    }
>   
>       decode_save_opc(ctx, 0);
>       addr = get_address(ctx, a->rs1, a->imm);
> diff --git a/target/riscv/tcg/insn_trans/trans_rvzfh.c.inc b/target/riscv/tcg/insn_trans/trans_rvzfh.c.inc
> index f36b46c2118..88711fb0769 100644
> --- a/target/riscv/tcg/insn_trans/trans_rvzfh.c.inc
> +++ b/target/riscv/tcg/insn_trans/trans_rvzfh.c.inc
> @@ -50,6 +50,9 @@ static bool trans_flh(DisasContext *ctx, arg_flh *a)
>       REQUIRE_ZFHMIN_OR_ZFBFMIN(ctx);
>   
>       memop |= ctx->mo_endianness;
> +    if (!ctx->cfg_ptr->ext_zicclsm) {
> +        memop |= MO_ALIGN;
> +    }
>       decode_save_opc(ctx, 0);
>       t0 = get_gpr(ctx, a->rs1, EXT_NONE);
>       if (a->imm) {
> @@ -75,6 +78,9 @@ static bool trans_fsh(DisasContext *ctx, arg_fsh *a)
>       REQUIRE_ZFHMIN_OR_ZFBFMIN(ctx);
>   
>       memop |= ctx->mo_endianness;
> +    if (!ctx->cfg_ptr->ext_zicclsm) {
> +        memop |= MO_ALIGN;
> +    }
>       decode_save_opc(ctx, 0);
>       t0 = get_gpr(ctx, a->rs1, EXT_NONE);
>       if (a->imm) {