Re: [PATCH v7 1/8] target/riscv: Add Zicclsm CPU option

Hi Daniel,

On Fri, Aug 7, 2026 at 9:49 PM Daniel Henrique Barboza <
[email protected]> wrote:

> Hi Frank!
>
> On 8/5/2026 1:43 PM, [email protected] wrote:
> > From: Frank Chang <[email protected]>
> >
> > Add Zicclsm CPU option so that user can turn on/off misaligned loads
> > and stores support.
> >
> > Signed-off-by: Frank Chang <[email protected]>
> > Reviewed-by: Max Chou <[email protected]>
> > Reviewed-by: Alistair Francis <[email protected]>
> > ---
> >   target/riscv/cpu_cfg_fields.h.inc | 2 ++
> >   1 file changed, 2 insertions(+)
> >
> > diff --git a/target/riscv/cpu_cfg_fields.h.inc
> b/target/riscv/cpu_cfg_fields.h.inc
> > index 9eb47af0a76..f8c27a574f8 100644
> > --- a/target/riscv/cpu_cfg_fields.h.inc
> > +++ b/target/riscv/cpu_cfg_fields.h.inc
> > @@ -139,6 +139,8 @@ BOOL_FIELD(has_priv_1_11)
> >   /* Always enabled for TCG if has_priv_1_11 */
> >   BOOL_FIELD(ext_ziccrse)
> >
> > +BOOL_FIELD(ext_zicclsm)
> > +
>
> This is a needed step but, as is, it's not adding a new CPU option for
> users as
> the commit msg says.  This is being done in patch 7.
>
> I think this change should be squashed into patch 2, where ext_zicclsm is
> being
> added in eligible CPUs.
>

Thanks for the review.

I've squashed patch 1 into patch 2 and sent out the v8 patchset:
https://lore.kernel.org/qemu-riscv/[email protected]/

Regards,
Frank Chang


>
>
> Thanks,
> Daniel
>
> >   /* Vendor-specific custom extensions */
> >   BOOL_FIELD(ext_xtheadba)
> >   BOOL_FIELD(ext_xtheadbb)
>
>