Re: [PATCH 22/56] disas/riscv: Handle c.slli imm != 0 during decode

On Sun, 2026-08-09 at 15:35 -0700, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <[email protected]>

Reviewed-by: Alistair Francis <[email protected]>

Alistair

> ---
>  disas/riscv.c | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/disas/riscv.c b/disas/riscv.c
> index a8fbefb9bd..77347b557d 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -1930,7 +1930,7 @@ static const rv_opcode_data rvi_opcode_data[] =
> {
>      { "c.bnez", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_bne,
> rv_op_bne,
>        rv_op_bne },
>      { "c.slli", rv_codec_ci_sh6, rv_fmt_rd_rs1_imm, NULL,
> rv_op_slli,
> -      rv_op_slli, rv_op_slli, rvcd_imm_nz },
> +      rv_op_slli, rv_op_slli },
>      { "c.fldsp", rv_codec_ci_ldsp, rv_fmt_frd_offset_rs1, NULL,
> rv_op_fld,
>        rv_op_fld, rv_op_fld },
>      { "c.lwsp", rv_codec_ci_lwsp, rv_fmt_rd_offset_rs1, NULL,
> rv_op_lw,
> @@ -3085,7 +3085,9 @@ static void decode_inst_opcode(rv_decode *dec,
> rv_isa isa)
>      case 2:
>          switch ((inst >> 13) & 0b111) {
>          case 0:
> -            op = rv_op_c_slli;
> +            if (isa != rv32 || (inst & 0x1000) == 0) {
> +                op = rv_op_c_slli; /* or unspecified HINT */
> +            }
>              break;
>          case 1:
>              if (isa == rv128) {