Re: [PATCH 25/56] disas/riscv: Unify decomp_rv{32,64,128}

On Sun, 2026-08-09 at 15:35 -0700, Richard Henderson wrote:
> We now distinguish compressed opcodes by isa during decode.
> Therefore we don't need 3 copies of decomp_*.
> 
> Signed-off-by: Richard Henderson <[email protected]>

Reviewed-by: Alistair Francis <[email protected]>

Alistair

> ---
>  disas/riscv.h |   4 +-
>  disas/riscv.c | 155 ++++++++++++++++--------------------------------
> --
>  2 files changed, 51 insertions(+), 108 deletions(-)
> 
> diff --git a/disas/riscv.h b/disas/riscv.h
> index 3909d73dd0..900363c603 100644
> --- a/disas/riscv.h
> +++ b/disas/riscv.h
> @@ -183,9 +183,7 @@ typedef struct {
>      rv_codec codec;
>      const char *format;
>      const rv_comp_data *pseudo;
> -    short decomp_rv32;
> -    short decomp_rv64;
> -    short decomp_rv128;
> +    rv_opcode decomp;
>  } rv_opcode_data;
>  
>  typedef struct {
> diff --git a/disas/riscv.c b/disas/riscv.c
> index 95957506bd..2e891f509e 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -1883,91 +1883,52 @@ static const rv_opcode_data rvi_opcode_data[]
> = {
>      { "fcvt.q.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1 },
>      { "fmv.x.q", rv_codec_r, rv_fmt_rd_frs1 },
>      { "fmv.q.x", rv_codec_r, rv_fmt_frd_rs1 },
> -    { "c.addi4spn", rv_codec_ciw_4spn, rv_fmt_rd_rs1_imm, NULL,
> rv_op_addi,
> -      rv_op_addi, rv_op_addi },
> -    { "c.fld", rv_codec_cl_ld, rv_fmt_frd_offset_rs1, NULL,
> rv_op_fld,
> -      rv_op_fld, 0 },
> -    { "c.lw", rv_codec_cl_lw, rv_fmt_rd_offset_rs1, NULL, rv_op_lw,
> rv_op_lw,
> -      rv_op_lw },
> -    { "c.flw", rv_codec_cl_lw, rv_fmt_frd_offset_rs1, NULL,
> rv_op_flw, 0, 0 },
> -    { "c.fsd", rv_codec_cs_sd, rv_fmt_frs2_offset_rs1, NULL,
> rv_op_fsd,
> -      rv_op_fsd, 0 },
> -    { "c.sw", rv_codec_cs_sw, rv_fmt_rs2_offset_rs1, NULL, rv_op_sw,
> rv_op_sw,
> -      rv_op_sw },
> -    { "c.fsw", rv_codec_cs_sw, rv_fmt_frs2_offset_rs1, NULL,
> rv_op_fsw, 0, 0 },
> +    { "c.addi4spn", rv_codec_ciw_4spn, rv_fmt_rd_rs1_imm, NULL,
> rv_op_addi },
> +    { "c.fld", rv_codec_cl_ld, rv_fmt_frd_offset_rs1, NULL,
> rv_op_fld },
> +    { "c.lw", rv_codec_cl_lw, rv_fmt_rd_offset_rs1, NULL, rv_op_lw
> },
> +    { "c.flw", rv_codec_cl_lw, rv_fmt_frd_offset_rs1, NULL,
> rv_op_flw },
> +    { "c.fsd", rv_codec_cs_sd, rv_fmt_frs2_offset_rs1, NULL,
> rv_op_fsd },
> +    { "c.sw", rv_codec_cs_sw, rv_fmt_rs2_offset_rs1, NULL, rv_op_sw
> },
> +    { "c.fsw", rv_codec_cs_sw, rv_fmt_frs2_offset_rs1, NULL,
> rv_op_fsw },
>      { },
> -    { "c.addi", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, rv_op_addi,
> rv_op_addi,
> -      rv_op_addi },
> -    { "c.jal", rv_codec_cj_jal, rv_fmt_rd_offset, NULL, rv_op_jal,
> 0, 0 },
> -    { "c.li", rv_codec_ci_li, rv_fmt_rd_rs1_imm, NULL, rv_op_addi,
> rv_op_addi,
> -      rv_op_addi },
> -    { "c.addi16sp", rv_codec_ci_16sp, rv_fmt_rd_rs1_imm, NULL,
> rv_op_addi,
> -      rv_op_addi, rv_op_addi },
> -    { "c.lui", rv_codec_ci_lui, rv_fmt_rd_uimm, NULL, rv_op_lui,
> rv_op_lui,
> -      rv_op_lui },
> -    { "c.srli", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL,
> rv_op_srli,
> -      rv_op_srli, rv_op_srli },
> -    { "c.srai", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL,
> rv_op_srai,
> -      rv_op_srai, rv_op_srai },
> -    { "c.andi", rv_codec_cb_imm, rv_fmt_rd_rs1_imm, NULL,
> rv_op_andi,
> -      rv_op_andi, rv_op_andi },
> -    { "c.sub", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_sub,
> rv_op_sub,
> -      rv_op_sub },
> -    { "c.xor", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_xor,
> rv_op_xor,
> -      rv_op_xor },
> -    { "c.or", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_or,
> rv_op_or,
> -      rv_op_or },
> -    { "c.and", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_and,
> rv_op_and,
> -      rv_op_and },
> -    { "c.subw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_subw,
> rv_op_subw,
> -      rv_op_subw },
> -    { "c.addw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_addw,
> rv_op_addw,
> -      rv_op_addw },
> -    { "c.j", rv_codec_cj, rv_fmt_rd_offset, NULL, rv_op_jal,
> rv_op_jal,
> -      rv_op_jal },
> -    { "c.beqz", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_beq,
> rv_op_beq,
> -      rv_op_beq },
> -    { "c.bnez", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_bne,
> rv_op_bne,
> -      rv_op_bne },
> -    { "c.slli", rv_codec_ci_sh6, rv_fmt_rd_rs1_imm, NULL,
> rv_op_slli,
> -      rv_op_slli, rv_op_slli },
> -    { "c.fldsp", rv_codec_ci_ldsp, rv_fmt_frd_offset_rs1, NULL,
> rv_op_fld,
> -      rv_op_fld, rv_op_fld },
> -    { "c.lwsp", rv_codec_ci_lwsp, rv_fmt_rd_offset_rs1, NULL,
> rv_op_lw,
> -      rv_op_lw, rv_op_lw },
> -    { "c.flwsp", rv_codec_ci_lwsp, rv_fmt_frd_offset_rs1, NULL,
> rv_op_flw, 0,
> -      0 },
> -    { "c.jr", rv_codec_cr_jr, rv_fmt_rd_rs1_offset, NULL,
> rv_op_jalr,
> -      rv_op_jalr, rv_op_jalr },
> -    { "c.mv", rv_codec_cr_mv, rv_fmt_rd_rs1_rs2, NULL, rv_op_addi,
> rv_op_addi,
> -      rv_op_addi },
> -    { "c.ebreak", rv_codec_ci_none, rv_fmt_none, NULL, rv_op_ebreak,
> -      rv_op_ebreak, rv_op_ebreak },
> -    { "c.jalr", rv_codec_cr_jalr, rv_fmt_rd_rs1_offset, NULL,
> rv_op_jalr,
> -      rv_op_jalr, rv_op_jalr },
> -    { "c.add", rv_codec_cr, rv_fmt_rd_rs1_rs2, NULL, rv_op_add,
> rv_op_add,
> -      rv_op_add },
> -    { "c.fsdsp", rv_codec_css_sdsp, rv_fmt_frs2_offset_rs1, NULL,
> rv_op_fsd,
> -      rv_op_fsd, rv_op_fsd },
> -    { "c.swsp", rv_codec_css_swsp, rv_fmt_rs2_offset_rs1, NULL,
> rv_op_sw,
> -      rv_op_sw, rv_op_sw },
> -    { "c.fswsp", rv_codec_css_swsp, rv_fmt_frs2_offset_rs1, NULL,
> rv_op_fsw, 0,
> -      0 },
> -    { "c.ld", rv_codec_cl_ld, rv_fmt_rd_offset_rs1, NULL, 0,
> rv_op_ld,
> -      rv_op_ld },
> -    { "c.sd", rv_codec_cs_sd, rv_fmt_rs2_offset_rs1, NULL, 0,
> rv_op_sd,
> -      rv_op_sd },
> -    { "c.addiw", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, 0,
> rv_op_addiw,
> -      rv_op_addiw },
> -    { "c.ldsp", rv_codec_ci_ldsp, rv_fmt_rd_offset_rs1, NULL, 0,
> rv_op_ld,
> -      rv_op_ld },
> -    { "c.sdsp", rv_codec_css_sdsp, rv_fmt_rs2_offset_rs1, NULL, 0,
> rv_op_sd,
> -      rv_op_sd },
> -    { "c.lq", rv_codec_cl_lq, rv_fmt_rd_offset_rs1, NULL, 0, 0,
> rv_op_lq },
> -    { "c.sq", rv_codec_cs_sq, rv_fmt_rs2_offset_rs1, NULL, 0, 0,
> rv_op_sq },
> -    { "c.lqsp", rv_codec_ci_lqsp, rv_fmt_rd_offset_rs1, NULL, 0, 0,
> rv_op_lq },
> -    { "c.sqsp", rv_codec_css_sqsp, rv_fmt_rs2_offset_rs1, NULL, 0,
> 0,
> -      rv_op_sq },
> +    { "c.addi", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, rv_op_addi },
> +    { "c.jal", rv_codec_cj_jal, rv_fmt_rd_offset, NULL, rv_op_jal },
> +    { "c.li", rv_codec_ci_li, rv_fmt_rd_rs1_imm, NULL, rv_op_addi },
> +    { "c.addi16sp", rv_codec_ci_16sp, rv_fmt_rd_rs1_imm, NULL,
> rv_op_addi },
> +    { "c.lui", rv_codec_ci_lui, rv_fmt_rd_uimm, NULL, rv_op_lui },
> +    { "c.srli", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srli
> },
> +    { "c.srai", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srai
> },
> +    { "c.andi", rv_codec_cb_imm, rv_fmt_rd_rs1_imm, NULL, rv_op_andi
> },
> +    { "c.sub", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_sub },
> +    { "c.xor", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_xor },
> +    { "c.or", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_or },
> +    { "c.and", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_and },
> +    { "c.subw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_subw },
> +    { "c.addw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_addw },
> +    { "c.j", rv_codec_cj, rv_fmt_rd_offset, NULL, rv_op_jal },
> +    { "c.beqz", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_beq
> },
> +    { "c.bnez", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_bne
> },
> +    { "c.slli", rv_codec_ci_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_slli
> },
> +    { "c.fldsp", rv_codec_ci_ldsp, rv_fmt_frd_offset_rs1, NULL,
> rv_op_fld },
> +    { "c.lwsp", rv_codec_ci_lwsp, rv_fmt_rd_offset_rs1, NULL,
> rv_op_lw },
> +    { "c.flwsp", rv_codec_ci_lwsp, rv_fmt_frd_offset_rs1, NULL,
> rv_op_flw },
> +    { "c.jr", rv_codec_cr_jr, rv_fmt_rd_rs1_offset, NULL, rv_op_jalr
> },
> +    { "c.mv", rv_codec_cr_mv, rv_fmt_rd_rs1_rs2, NULL, rv_op_addi },
> +    { "c.ebreak", rv_codec_ci_none, rv_fmt_none, NULL, rv_op_ebreak
> },
> +    { "c.jalr", rv_codec_cr_jalr, rv_fmt_rd_rs1_offset, NULL,
> rv_op_jalr },
> +    { "c.add", rv_codec_cr, rv_fmt_rd_rs1_rs2, NULL, rv_op_add },
> +    { "c.fsdsp", rv_codec_css_sdsp, rv_fmt_frs2_offset_rs1, NULL,
> rv_op_fsd },
> +    { "c.swsp", rv_codec_css_swsp, rv_fmt_rs2_offset_rs1, NULL,
> rv_op_sw },
> +    { "c.fswsp", rv_codec_css_swsp, rv_fmt_frs2_offset_rs1, NULL,
> rv_op_fsw },
> +    { "c.ld", rv_codec_cl_ld, rv_fmt_rd_offset_rs1, NULL, rv_op_ld
> },
> +    { "c.sd", rv_codec_cs_sd, rv_fmt_rs2_offset_rs1, NULL,  rv_op_sd
> },
> +    { "c.addiw", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, rv_op_addiw
> },
> +    { "c.ldsp", rv_codec_ci_ldsp, rv_fmt_rd_offset_rs1, NULL,
> rv_op_ld },
> +    { "c.sdsp", rv_codec_css_sdsp, rv_fmt_rs2_offset_rs1, NULL,
> rv_op_sd },
> +    { "c.lq", rv_codec_cl_lq, rv_fmt_rd_offset_rs1, NULL, rv_op_lq
> },
> +    { "c.sq", rv_codec_cs_sq, rv_fmt_rs2_offset_rs1, NULL, rv_op_sq
> },
> +    { "c.lqsp", rv_codec_ci_lqsp, rv_fmt_rd_offset_rs1, NULL,
> rv_op_lq },
> +    { "c.sqsp", rv_codec_css_sqsp, rv_fmt_rs2_offset_rs1, NULL,
> rv_op_sq },
>      { "nop", rv_codec_i, rv_fmt_none },
>      { "mv", rv_codec_i, rv_fmt_rd_rs1 },
>      { "not", rv_codec_i, rv_fmt_rd_rs1 },
> @@ -2649,10 +2610,8 @@ static const rv_opcode_data rvi_opcode_data[]
> = {
>      { "ssrdp", rv_codec_r, rv_fmt_rd },
>      { "ssamoswap.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
>      { "ssamoswap.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1 },
> -    { "c.sspush", rv_codec_cmop_ss, rv_fmt_rs2, NULL, rv_op_sspush,
> -      rv_op_sspush, 0 },
> -    { "c.sspopchk", rv_codec_cmop_ss, rv_fmt_rs1, NULL,
> rv_op_sspopchk,
> -      rv_op_sspopchk, 0 },
> +    { "c.sspush", rv_codec_cmop_ss, rv_fmt_rs2, NULL, rv_op_sspush
> },
> +    { "c.sspopchk", rv_codec_cmop_ss, rv_fmt_rs1, NULL,
> rv_op_sspopchk },
>     { "cbo.inval", rv_codec_r, rv_fmt_rs1 },
>     { "cbo.clean", rv_codec_r, rv_fmt_rs1 },
>     { "cbo.flush", rv_codec_r, rv_fmt_rs1 },
> @@ -5397,24 +5356,10 @@ static const rv_opcode_data
> *decode_inst_lift_pseudo(rv_decode *dec,
>  
>  /* decompress instruction */
>  
> -static const rv_opcode_data *decode_inst_decompress(rv_decode *dec,
> rv_isa isa,
> +static const rv_opcode_data *decode_inst_decompress(rv_decode *dec,
>                                                      const
> rv_opcode_data *op)
>  {
> -    int decomp_op;
> -
> -    switch (isa) {
> -    case rv32:
> -        decomp_op = op->decomp_rv32;
> -        break;
> -    case rv64:
> -        decomp_op = op->decomp_rv64;
> -        break;
> -    case rv128:
> -        decomp_op = op->decomp_rv128;
> -        break;
> -    default:
> -        g_assert_not_reached();
> -    }
> +    int decomp_op = op->decomp;
>  
>      if (decomp_op != rv_op_illegal) {
>          dec->op = decomp_op;
> @@ -5473,7 +5418,7 @@ static GString *disasm_inst(rv_isa isa,
> uint64_t pc, rv_inst inst,
>  
>      op = &dec.opcode_data[dec.op];
>      decode_inst_operands(&dec, isa, op);
> -    op = decode_inst_decompress(&dec, isa, op);
> +    op = decode_inst_decompress(&dec, op);
>      op = decode_inst_lift_pseudo(&dec, op);
>      return format_inst(24, &dec, op);
>  }