Re: [PATCH 43/56] disas/riscv: Fix isa decoding of rev8
Alistair <[email protected]>
| Newsgroups | org.nongnu.qemu-riscv,org.nongnu.qemu-devel |
|---|---|
| Message-ID | <[email protected]> |
On Sun, 2026-08-09 at 15:35 -0700, Richard Henderson wrote: > The encoding of rev8 is different for rv32 and rv64. > > Cc: [email protected] > Fixes: 02c1b569a15 ("disas/riscv: Add Zb[abcs] instructions") > Signed-off-by: Richard Henderson <[email protected]> Reviewed-by: Alistair Francis <[email protected]> Alistair > --- > disas/riscv.c | 12 ++++++++++-- > 1 file changed, 10 insertions(+), 2 deletions(-) > > diff --git a/disas/riscv.c b/disas/riscv.c > index 9442a6c115..4141741d79 100644 > --- a/disas/riscv.c > +++ b/disas/riscv.c > @@ -3292,8 +3292,16 @@ static const rv_opcode_data > *decode_inst_opcode(rv_decode *dec, rv_isa isa) > case 0b01100: op = rv_op_rori; break; > case 0b01101: > switch ((inst >> 20) & 0b1111111) { > - case 0b0011000: op = rv_op_rev8; break; > - case 0b0111000: op = rv_op_rev8; break; > + case 0b0011000: > + if (isa == rv32) { > + op = rv_op_rev8; > + } > + break; > + case 0b0111000: > + if (isa == rv64) { > + op = rv_op_rev8; > + } > + break; > case 0b0000111: op = rv_op_brev8; break; > } > break;