Re: [PATCH 51/56] disas/riscv: Merge all mop.rr.n to one pattern
Alistair <[email protected]>
| Newsgroups | org.nongnu.qemu-riscv,org.nongnu.qemu-devel |
|---|---|
| Message-ID | <[email protected]> |
On Sun, 2026-08-09 at 15:35 -0700, Richard Henderson wrote: > Avoid performing arithmetic on rv_op_mop_rr_0. > Treat the 'n' as an immediate. > Create a codec and format to match. > > Signed-off-by: Richard Henderson <[email protected]> Reviewed-by: Alistair Francis <[email protected]> Alistair > --- > disas/riscv.h | 2 ++ > disas/riscv.c | 13 ++++++++++++- > disas/riscv-op.c.inc | 9 +-------- > 3 files changed, 15 insertions(+), 9 deletions(-) > > diff --git a/disas/riscv.h b/disas/riscv.h > index b47a7f0150..47647f750f 100644 > --- a/disas/riscv.h > +++ b/disas/riscv.h > @@ -161,6 +161,7 @@ typedef enum { > rv_codec_lp, > rv_codec_cmop_ss, > rv_codec_mop_r, > + rv_codec_mop_rr, > } rv_codec; > > /* structures */ > @@ -286,5 +287,6 @@ typedef struct { > #define rv_fmt_rd2_imm "O\t0,2,(1),i" > #define rv_fmt_fli "O\t3,h" > #define rv_fmt_mop_r "O.i\t0,1" > +#define rv_fmt_mop_rr "O.i\t0,1,2" > > #endif /* DISAS_RISCV_H */ > diff --git a/disas/riscv.c b/disas/riscv.c > index 450a5c8142..6ec62a5830 100644 > --- a/disas/riscv.c > +++ b/disas/riscv.c > @@ -650,6 +650,11 @@ static uint32_t operand_mop_r_imm(rv_inst inst) > extract32(inst, 20, 2); > } > > +static uint32_t operand_mop_rr_imm(rv_inst inst) > +{ > + return (extract32(inst, 30, 1) << 2) | extract32(inst, 26, 2); > +} > + > /* instruction metadata */ > > static const rv_opcode_data rvi_opcode_data[] = { > @@ -2572,7 +2577,7 @@ static const rv_opcode_data > *decode_inst_opcode(rv_decode *dec, rv_isa isa) > == 0b1000001) { > imm_mop3 = deposit32(extract32(inst, 26, 2), > 2, 1, extract32(inst, > 30, 1)); > - op = rv_op_mop_rr_0 + imm_mop3; > + op = rv_op_mop_rr; > /* if zicfiss enabled and mop3 is shadow > stack */ > if (dec->cfg->ext_zicfiss && > ((imm_mop3 & 0b111) == 0b111)) { > @@ -3061,6 +3066,12 @@ static void decode_inst_operands(rv_decode > *dec, rv_isa isa, > dec->rs1 = operand_rs1(inst); > dec->imm = operand_mop_r_imm(inst); > break; > + case rv_codec_mop_rr: > + dec->rd = operand_rd(inst); > + dec->rs1 = operand_rs1(inst); > + dec->rs2 = operand_rs2(inst); > + dec->imm = operand_mop_rr_imm(inst); > + break; > default: > g_assert_not_reached(); > } > diff --git a/disas/riscv-op.c.inc b/disas/riscv-op.c.inc > index 222d249a70..2100e54475 100644 > --- a/disas/riscv-op.c.inc > +++ b/disas/riscv-op.c.inc > @@ -874,14 +874,7 @@ OP(amocas_w, "amocas.w", rv_codec_r_a, > rv_fmt_aqrl_rd_rs2_rs1) > OP(amocas_d, "amocas.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1) > OP(amocas_q, "amocas.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1) > OP(mop_r, "mop.r", rv_codec_mop_r, rv_fmt_mop_r) > -OP(mop_rr_0, "mop.rr.0", rv_codec_r, rv_fmt_rd_rs1_rs2) > -OP(mop_rr_1, "mop.rr.1", rv_codec_r, rv_fmt_rd_rs1_rs2) > -OP(mop_rr_2, "mop.rr.2", rv_codec_r, rv_fmt_rd_rs1_rs2) > -OP(mop_rr_3, "mop.rr.3", rv_codec_r, rv_fmt_rd_rs1_rs2) > -OP(mop_rr_4, "mop.rr.4", rv_codec_r, rv_fmt_rd_rs1_rs2) > -OP(mop_rr_5, "mop.rr.5", rv_codec_r, rv_fmt_rd_rs1_rs2) > -OP(mop_rr_6, "mop.rr.6", rv_codec_r, rv_fmt_rd_rs1_rs2) > -OP(mop_rr_7, "mop.rr.7", rv_codec_r, rv_fmt_rd_rs1_rs2) > +OP(mop_rr, "mop.rr", rv_codec_mop_rr, rv_fmt_mop_rr) > OP(c_mop_1, "c.mop.1", rv_codec_ci_none, rv_fmt_none) > OP(c_mop_3, "c.mop.3", rv_codec_ci_none, rv_fmt_none) > OP(c_mop_5, "c.mop.5", rv_codec_ci_none, rv_fmt_none)