[PATCH v2 38/52] disas/riscv: Fix rv32 encoding of zext.h
Richard Henderson <[email protected]>
| Newsgroups | org.nongnu.qemu-riscv,org.nongnu.qemu-devel |
|---|---|
| Message-ID | <[email protected]> |
For rv64, pack with rs2 = 0 does not encode zext.h. Cc: [email protected] Fixes: 02c1b569a15 ("disas/riscv: Add Zb[abcs] instructions") Reviewed-by: Alistair Francis <[email protected]> Signed-off-by: Richard Henderson <[email protected]> --- disas/riscv.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/disas/riscv.c b/disas/riscv.c index e650ad7688..5624e7f60a 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -3506,9 +3506,10 @@ static const rv_opcode_data *decode_inst_opcode(rv_decode *dec, rv_isa isa) case 14: op = rv_op_rem; break; case 15: op = rv_op_remu; break; case 36: - switch ((inst >> 20) & 0b11111) { - case 0: op = rv_op_zext_h; break; - default: op = rv_op_pack; break; + if (isa == rv32 && !((inst >> 20) & 0b11111)) { + op = rv_op_zext_h; + } else { + op = rv_op_pack; } break; case 39: op = rv_op_packh; break; -- 2.43.0