Re: [PATCH 1/2] riscv: csr: do not drop C bit on misa write

On Thu, 6 Aug 2026 at 23:07, Vladimir Isaev <[email protected]> wrote:
>
> According to spec:
> > Writing misa may increase IALIGN, e.g., by disabling the "C" extension.
> > If an instruction that would write misa increases IALIGN, and the
> > subsequent instruction’s address is not IALIGN-bit aligned, the
> > write to misa is suppressed, leaving misa unchanged.
>
> So attempt to disable C extension if next instruction is not aligned should not
> change the misa.
>
> Signed-off-by: Vladimir Isaev <[email protected]>
> ---
>  target/riscv/tcg/csr.c | 7 ++++---
>  1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/tcg/csr.c b/target/riscv/tcg/csr.c
> index 36f2004bc5..58c206c1fa 100644
> --- a/target/riscv/tcg/csr.c
> +++ b/target/riscv/tcg/csr.c
> @@ -2182,9 +2182,10 @@ static RISCVException write_misa(CPURISCVState *env, int csrno,
>      /* Mask extensions that are not supported by this hart */
>      val &= env->misa_ext_mask;
>
> -    /* Suppress 'C' if next instruction is not aligned. */
> -    if ((val & RVC) && (get_next_pc(env, ra) & 3) != 0) {
> -        val &= ~RVC;
> +    /* drop write if RVC is cleared and next instruction is not aligned */
> +    if ((env->misa_ext & RVC) && !(val & RVC) &&
> +         (get_next_pc(env, ra) & 3) != 0) {
> +        return RISCV_EXCP_NONE;
>      }

I thought we'd already fixed this so I went hunting. This is similar
to Nick's patch:

https://lore.kernel.org/qemu-devel/acTSDKzeEb3bbv08@lima-default/

I think the conclusion there was to additionally check ra, and do
a qemu_log_mask(LOG_GUEST_ERROR, ...)

I don't think he got around to sending the next version of that series.

Cheers,

Joel