[PATCH 00/23] target/riscv: Reorg vector load/store

Hi all,

I'm working on a reorg of the probe_access set of functions and in
the process I discovered probe_pages() within riscv vector_helper.c.

The short story there is that probe_pages() is broken.  I had several
attempts to fix it before tackling the wider problem: there are way
too many probes going on, mostly from vext_ldff.  There was a real
lack of using the result of one page probe to cover any other elements
within the same page.

So this is an attempt to reorganize things such that there's one
probe per page as we step through vstart -> vl.  But since I touched
so much code, of course I saw other bits that could use improvement.

In particular, Frank, is the location of the alignment test you added,
which is in riscv-to-apply.next but not yet mainline.  I *think* it
is at the wrong place.  Also, it's unclear to me how/where it applies
to the fault-on-first instructions. I've moved it first, before any
page probing, as we would get along the tlb slow path.  I believe I
won't trigger an alignment fault if all vector elements are masked.
We can compute MemOpIdx per vector, not per element.

Thanks for the system mode alignment test, btw.  :-)

Anyway, thoughts?


r~


PS: Based-on riscv-to-apply.next, obvs.


Richard Henderson (23):
  target/riscv: Split out vext_set_nf_elems_1s
  target/riscv: Hoist vma check out of vext_set_tail_elems_1s
  target/riscv: Split out vext_ldst_nf_tlb
  target/riscv: Split out vext_ldst_nf_host
  target/riscv: Add evl argument to vext_ldst_elem_fn_host
  target/riscv: Drop is_load parameter from vext_continuous_ldst_tlb
  target/riscv: Remove vext_continuous_ldst_tlb
  target/riscv: Move misalignment check out of vext_page_ldst_us
  target/riscv: Split out vext_page_ldst_us_{host,tlb}
  target/riscv: Rewrite vext_ldst_us
  target/riscv: Rewrite vext_ldff
  target/riscv: Split out vext_ldst_us_desc
  target/riscv: Use vext_ldst_us in vext_ldst_whole
  target/riscv: Mark VSTART_CHECK_EARLY_EXIT unlikely
  target/riscv: Remove unused VDATA,WD
  target/riscv: Add MEM_IDX, BSWAP, ALIGN to VDATA
  target/riscv: Pass MemOpIdx to vext_ldst_us
  target/riscv: Build MemOpIdx to vext_ldff
  target/riscv: Pass MemOpIdx to vext_ldst_elem_fn_tlb
  target/riscv: Use FLATTEN rather than ALWAYS_INLINE for vector ldst
  target/riscv: Drop v0 argument from gen_helper_ldst_us
  target/riscv: Drop v0 argument from gen_helper_ldst_stride
  target/riscv: Drop v0 argument from gen_helper_ldst_index

 target/riscv/helper.h                       |  124 +--
 target/riscv/internals.h                    |    4 +-
 target/riscv/tcg/vector_internals.h         |    2 +-
 target/riscv/tcg/vector_helper.c            | 1010 ++++++++++---------
 target/riscv/tcg/insn_trans/trans_rvv.c.inc |   77 +-
 5 files changed, 627 insertions(+), 590 deletions(-)

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2.43.0