[PATCH 21/23] target/riscv: Drop v0 argument from gen_helper_ldst_us
Richard Henderson <[email protected]>
| Newsgroups | org.nongnu.qemu-riscv,org.nongnu.qemu-devel |
|---|---|
| Message-ID | <[email protected]> |
Since we're also passing env, v0 is always env->vreg. Signed-off-by: Richard Henderson <[email protected]> --- target/riscv/helper.h | 44 ++++++++++----------- target/riscv/tcg/vector_helper.c | 36 +++++++++-------- target/riscv/tcg/insn_trans/trans_rvv.c.inc | 25 ++++-------- 3 files changed, 48 insertions(+), 57 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 542b7c264f..ffd759aef3 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -162,24 +162,24 @@ DEF_HELPER_FLAGS_3(hyp_hsv_d, TCG_CALL_NO_WG, void, env, tl, tl) /* Vector functions */ DEF_HELPER_4(vsetvl, tl, env, tl, tl, tl) -DEF_HELPER_5(vle8_v, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vle16_v, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vle32_v, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vle64_v, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vle8_v_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vle16_v_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vle32_v_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vle64_v_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vse8_v, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vse16_v, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vse32_v, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vse64_v, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vse8_v_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vse16_v_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vse32_v_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vse64_v_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlm_v, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vsm_v, void, ptr, ptr, tl, env, i32) +DEF_HELPER_4(vle8_v, void, ptr, tl, env, i32) +DEF_HELPER_4(vle16_v, void, ptr, tl, env, i32) +DEF_HELPER_4(vle32_v, void, ptr, tl, env, i32) +DEF_HELPER_4(vle64_v, void, ptr, tl, env, i32) +DEF_HELPER_4(vle8_v_mask, void, ptr, tl, env, i32) +DEF_HELPER_4(vle16_v_mask, void, ptr, tl, env, i32) +DEF_HELPER_4(vle32_v_mask, void, ptr, tl, env, i32) +DEF_HELPER_4(vle64_v_mask, void, ptr, tl, env, i32) +DEF_HELPER_4(vse8_v, void, ptr, tl, env, i32) +DEF_HELPER_4(vse16_v, void, ptr, tl, env, i32) +DEF_HELPER_4(vse32_v, void, ptr, tl, env, i32) +DEF_HELPER_4(vse64_v, void, ptr, tl, env, i32) +DEF_HELPER_4(vse8_v_mask, void, ptr, tl, env, i32) +DEF_HELPER_4(vse16_v_mask, void, ptr, tl, env, i32) +DEF_HELPER_4(vse32_v_mask, void, ptr, tl, env, i32) +DEF_HELPER_4(vse64_v_mask, void, ptr, tl, env, i32) +DEF_HELPER_4(vlm_v, void, ptr, tl, env, i32) +DEF_HELPER_4(vsm_v, void, ptr, tl, env, i32) DEF_HELPER_6(vlse8_v, void, ptr, ptr, tl, tl, env, i32) DEF_HELPER_6(vlse16_v, void, ptr, ptr, tl, tl, env, i32) DEF_HELPER_6(vlse32_v, void, ptr, ptr, tl, tl, env, i32) @@ -220,10 +220,10 @@ DEF_HELPER_6(vsxei64_8_v, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vsxei64_16_v, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vsxei64_32_v, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vsxei64_64_v, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_5(vle8ff_v, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vle16ff_v, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vle32ff_v, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vle64ff_v, void, ptr, ptr, tl, env, i32) +DEF_HELPER_4(vle8ff_v, void, ptr, tl, env, i32) +DEF_HELPER_4(vle16ff_v, void, ptr, tl, env, i32) +DEF_HELPER_4(vle32ff_v, void, ptr, tl, env, i32) +DEF_HELPER_4(vle64ff_v, void, ptr, tl, env, i32) DEF_HELPER_4(vl1re8_v, void, ptr, tl, env, i32) DEF_HELPER_4(vl1re16_v, void, ptr, tl, env, i32) diff --git a/target/riscv/tcg/vector_helper.c b/target/riscv/tcg/vector_helper.c index 2a24e15a31..2548ad9c2c 100644 --- a/target/riscv/tcg/vector_helper.c +++ b/target/riscv/tcg/vector_helper.c @@ -292,11 +292,12 @@ static void vext_ldst_nf_tlb(CPURISCVState *env, void *vd, target_ulong addr, * stride: access vector element from strided memory */ static void -vext_ldst_stride(void *vd, void *v0, target_ulong base, target_ulong stride, +vext_ldst_stride(void *vd, target_ulong base, target_ulong stride, CPURISCVState *env, uint32_t desc, uint32_t vm, vext_ldst_elem_fn_tlb *ldst_elem, uint32_t log2_esz, uintptr_t ra) { + void *v0 = env->vreg; uint32_t nf = vext_nf(desc); uint32_t max_elems = vext_max_elems(desc, log2_esz); uint32_t esz = 1 << log2_esz; @@ -326,7 +327,7 @@ void HELPER(NAME)(void *vd, void * v0, target_ulong base, \ uint32_t desc) \ { \ uint32_t vm = vext_vm(desc); \ - vext_ldst_stride(vd, v0, base, stride, env, desc, vm, LOAD_FN, \ + vext_ldst_stride(vd, base, stride, env, desc, vm, LOAD_FN, \ ctzl(sizeof(ETYPE)), GETPC()); \ } @@ -341,7 +342,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong base, \ uint32_t desc) \ { \ uint32_t vm = vext_vm(desc); \ - vext_ldst_stride(vd, v0, base, stride, env, desc, vm, STORE_FN, \ + vext_ldst_stride(vd, base, stride, env, desc, vm, STORE_FN, \ ctzl(sizeof(ETYPE)), GETPC()); \ } @@ -523,14 +524,14 @@ vext_ldst_us_desc(void *vd, target_ulong base, CPURISCVState *env, */ #define GEN_VEXT_LD_US(NAME, ETYPE, LOAD_FN_TLB, LOAD_FN_HOST) \ -QEMU_FLATTEN void HELPER(NAME##_mask)(void *vd, void *v0, \ - target_ulong base, CPURISCVState *env, uint32_t desc) \ +QEMU_FLATTEN void HELPER(NAME##_mask)(void *vd, target_ulong base, \ + CPURISCVState *env, uint32_t desc) \ { \ uint32_t stride = vext_nf(desc) << ctzl(sizeof(ETYPE)); \ - vext_ldst_stride(vd, v0, base, stride, env, desc, false, \ + vext_ldst_stride(vd, base, stride, env, desc, false, \ LOAD_FN_TLB, ctzl(sizeof(ETYPE)), GETPC()); \ } \ -QEMU_FLATTEN void HELPER(NAME)(void *vd, void *v0, target_ulong base, \ +QEMU_FLATTEN void HELPER(NAME)(void *vd, target_ulong base, \ CPURISCVState *env, uint32_t desc) \ { \ vext_ldst_us_desc(vd, base, env, desc, LOAD_FN_TLB, LOAD_FN_HOST, \ @@ -543,15 +544,15 @@ GEN_VEXT_LD_US(vle32_v, int32_t, lde_w_tlb, lde_w_host) GEN_VEXT_LD_US(vle64_v, int64_t, lde_d_tlb, lde_d_host) #define GEN_VEXT_ST_US(NAME, ETYPE, STORE_FN_TLB, STORE_FN_HOST) \ -QEMU_FLATTEN void HELPER(NAME##_mask)(void *vd, void *v0, \ - target_ulong base, CPURISCVState *env, uint32_t desc) \ +QEMU_FLATTEN void HELPER(NAME##_mask)(void *vd, target_ulong base, \ + CPURISCVState *env, uint32_t desc) \ { \ uint32_t stride = vext_nf(desc) << ctzl(sizeof(ETYPE)); \ - vext_ldst_stride(vd, v0, base, stride, env, desc, false, \ + vext_ldst_stride(vd, base, stride, env, desc, false, \ STORE_FN_TLB, ctzl(sizeof(ETYPE)), GETPC()); \ } \ -QEMU_FLATTEN void HELPER(NAME)(void *vd, void *v0, target_ulong base, \ - CPURISCVState *env, uint32_t desc) \ +QEMU_FLATTEN void HELPER(NAME)(void *vd, target_ulong base, \ + CPURISCVState *env, uint32_t desc) \ { \ vext_ldst_us_desc(vd, base, env, desc, STORE_FN_TLB, STORE_FN_HOST, \ ctzl(sizeof(ETYPE)), env->vl, GETPC(), false); \ @@ -565,7 +566,7 @@ GEN_VEXT_ST_US(vse64_v, int64_t, ste_d_tlb, ste_d_host) /* * unit stride mask load and store, EEW = 1 */ -QEMU_FLATTEN void HELPER(vlm_v)(void *vd, void *v0, target_ulong base, +QEMU_FLATTEN void HELPER(vlm_v)(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc) { /* evl = ceil(vl/8) */ @@ -574,7 +575,7 @@ QEMU_FLATTEN void HELPER(vlm_v)(void *vd, void *v0, target_ulong base, 0, evl, GETPC(), true); } -QEMU_FLATTEN void HELPER(vsm_v)(void *vd, void *v0, target_ulong base, +QEMU_FLATTEN void HELPER(vsm_v)(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc) { /* evl = ceil(vl/8) */ @@ -692,10 +693,11 @@ GEN_VEXT_ST_INDEX(vsxei64_64_v, int64_t, idx_d, ste_d_tlb) * unit-stride fault-only-fisrt load instructions */ static void -vext_ldff(void *vd, void *v0, target_ulong base, CPURISCVState *env, +vext_ldff(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc, vext_ldst_elem_fn_tlb *ldst_tlb, vext_ldst_elem_fn_host *ldst_host, uint32_t log2_esz, uintptr_t ra) { + void *v0 = env->vreg; uint32_t i = env->vstart, vl = env->vl; uint32_t nf = vext_nf(desc); uint32_t vm = vext_vm(desc); @@ -925,10 +927,10 @@ vext_ldff(void *vd, void *v0, target_ulong base, CPURISCVState *env, } #define GEN_VEXT_LDFF(NAME, ETYPE, LOAD_FN_TLB, LOAD_FN_HOST) \ -QEMU_FLATTEN void HELPER(NAME)(void *vd, void *v0, target_ulong base, \ +QEMU_FLATTEN void HELPER(NAME)(void *vd, target_ulong base, \ CPURISCVState *env, uint32_t desc) \ { \ - vext_ldff(vd, v0, base, env, desc, LOAD_FN_TLB, \ + vext_ldff(vd, base, env, desc, LOAD_FN_TLB, \ LOAD_FN_HOST, ctzl(sizeof(ETYPE)), GETPC()); \ } diff --git a/target/riscv/tcg/insn_trans/trans_rvv.c.inc b/target/riscv/tcg/insn_trans/trans_rvv.c.inc index 3916236762..3d32564660 100644 --- a/target/riscv/tcg/insn_trans/trans_rvv.c.inc +++ b/target/riscv/tcg/insn_trans/trans_rvv.c.inc @@ -690,8 +690,7 @@ static uint8_t vext_get_emul(DisasContext *s, uint8_t eew) /* *** unit stride load and store */ -typedef void gen_helper_ldst_us(TCGv_ptr, TCGv_ptr, TCGv, - TCGv_env, TCGv_i32); +typedef void gen_helper_ldst_us(TCGv_ptr, TCGv, TCGv_env, TCGv_i32); static uint32_t vdata_add_memopidx(DisasContext *s, uint32_t data) { @@ -705,14 +704,10 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data, gen_helper_ldst_us *fn, DisasContext *s, bool is_store) { - TCGv_ptr dest, mask; - TCGv base; + TCGv_ptr dest = tcg_temp_new_ptr(); + TCGv base = get_gpr(s, rs1, EXT_NONE); TCGv_i32 desc; - dest = tcg_temp_new_ptr(); - mask = tcg_temp_new_ptr(); - base = get_gpr(s, rs1, EXT_NONE); - /* * As simd_desc supports at most 2048 bytes, and in this implementation, * the max vector group length is 4096 bytes. So split it into two parts. @@ -725,7 +720,6 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data, s->cfg_ptr->vlenb, data)); tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, vd)); - tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0)); /* * According to the specification @@ -745,7 +739,7 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data, mark_vs_dirty(s); - fn(dest, mask, base, tcg_env, desc); + fn(dest, base, tcg_env, desc); if (!is_store && s->ztso) { tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); @@ -1133,22 +1127,17 @@ GEN_VEXT_TRANS(vsxei64_v, MO_64, rnfvm, st_index_op, st_index_check) static bool ldff_trans(uint32_t vd, uint32_t rs1, uint32_t data, gen_helper_ldst_us *fn, DisasContext *s) { - TCGv_ptr dest, mask; - TCGv base; + TCGv_ptr dest = tcg_temp_new_ptr(); + TCGv base = get_gpr(s, rs1, EXT_NONE); TCGv_i32 desc; - dest = tcg_temp_new_ptr(); - mask = tcg_temp_new_ptr(); - base = get_gpr(s, rs1, EXT_NONE); - data = vdata_add_memopidx(s, data); desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlenb, s->cfg_ptr->vlenb, data)); tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, vd)); - tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0)); - fn(dest, mask, base, tcg_env, desc); + fn(dest, base, tcg_env, desc); finalize_rvv_inst(s); -- 2.43.0