[PATCH 12/23] target/riscv: Split out vext_ldst_us_desc
Richard Henderson <[email protected]>
| Newsgroups | org.nongnu.qemu-riscv,org.nongnu.qemu-devel |
|---|---|
| Message-ID | <[email protected]> |
Rename vext_ldst_us to vext_ldst_us_desc and split out a new vext_ldst_us that doesn't use 'desc'. Signed-off-by: Richard Henderson <[email protected]> --- target/riscv/tcg/vector_helper.c | 38 ++++++++++++++++++++------------ 1 file changed, 24 insertions(+), 14 deletions(-) diff --git a/target/riscv/tcg/vector_helper.c b/target/riscv/tcg/vector_helper.c index b482537f40..abb1ebcb43 100644 --- a/target/riscv/tcg/vector_helper.c +++ b/target/riscv/tcg/vector_helper.c @@ -478,15 +478,14 @@ static void vext_test_alignment(CPURISCVState *env, vaddr addr, uint32_t esz, } static inline QEMU_ALWAYS_INLINE void -vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc, +vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, + uint32_t log2_esz, uint32_t nf, uint32_t evl, + uint32_t max_elems, bool vma, vext_ldst_elem_fn_tlb *ldst_tlb, - vext_ldst_elem_fn_host *ldst_host, uint32_t log2_esz, - uint32_t evl, uintptr_t ra, bool is_load) + vext_ldst_elem_fn_host *ldst_host, + uintptr_t ra, bool is_load) { target_ulong elems, addr, last, last_in_page, page_split; - uint32_t nf = vext_nf(desc); - uint32_t vma = vext_vma(desc); - uint32_t max_elems = vext_max_elems(desc, log2_esz); uint32_t esz = 1 << log2_esz; uint32_t msize = nf * esz; int mmu_index = riscv_env_mmu_index(env, false); @@ -579,6 +578,17 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc, } } +static inline QEMU_ALWAYS_INLINE void +vext_ldst_us_desc(void *vd, target_ulong base, CPURISCVState *env, + uint32_t desc, vext_ldst_elem_fn_tlb *ldst_tlb, + vext_ldst_elem_fn_host *ldst_host, uint32_t log2_esz, + uint32_t evl, uintptr_t ra, bool is_load) +{ + vext_ldst_us(vd, base, env, log2_esz, vext_nf(desc), evl, + vext_max_elems(desc, log2_esz), vext_vma(desc), + ldst_tlb, ldst_host, ra, is_load); +} + /* * masked unit-stride load and store operation will be a special case of * stride, stride = NF * sizeof (ETYPE) @@ -596,8 +606,8 @@ void HELPER(NAME##_mask)(void *vd, void *v0, target_ulong base, \ void HELPER(NAME)(void *vd, void *v0, target_ulong base, \ CPURISCVState *env, uint32_t desc) \ { \ - vext_ldst_us(vd, base, env, desc, LOAD_FN_TLB, LOAD_FN_HOST, \ - ctzl(sizeof(ETYPE)), env->vl, GETPC(), true); \ + vext_ldst_us_desc(vd, base, env, desc, LOAD_FN_TLB, LOAD_FN_HOST, \ + ctzl(sizeof(ETYPE)), env->vl, GETPC(), true); \ } GEN_VEXT_LD_US(vle8_v, int8_t, lde_b_tlb, lde_b_host) @@ -617,8 +627,8 @@ void HELPER(NAME##_mask)(void *vd, void *v0, target_ulong base, \ void HELPER(NAME)(void *vd, void *v0, target_ulong base, \ CPURISCVState *env, uint32_t desc) \ { \ - vext_ldst_us(vd, base, env, desc, STORE_FN_TLB, STORE_FN_HOST, \ - ctzl(sizeof(ETYPE)), env->vl, GETPC(), false); \ + vext_ldst_us_desc(vd, base, env, desc, STORE_FN_TLB, STORE_FN_HOST, \ + ctzl(sizeof(ETYPE)), env->vl, GETPC(), false); \ } GEN_VEXT_ST_US(vse8_v, int8_t, ste_b_tlb, ste_b_host) @@ -634,8 +644,8 @@ void HELPER(vlm_v)(void *vd, void *v0, target_ulong base, { /* evl = ceil(vl/8) */ uint8_t evl = (env->vl + 7) >> 3; - vext_ldst_us(vd, base, env, desc, lde_b_tlb, lde_b_host, - 0, evl, GETPC(), true); + vext_ldst_us_desc(vd, base, env, desc, lde_b_tlb, lde_b_host, + 0, evl, GETPC(), true); } void HELPER(vsm_v)(void *vd, void *v0, target_ulong base, @@ -643,8 +653,8 @@ void HELPER(vsm_v)(void *vd, void *v0, target_ulong base, { /* evl = ceil(vl/8) */ uint8_t evl = (env->vl + 7) >> 3; - vext_ldst_us(vd, base, env, desc, ste_b_tlb, ste_b_host, - 0, evl, GETPC(), false); + vext_ldst_us_desc(vd, base, env, desc, ste_b_tlb, ste_b_host, + 0, evl, GETPC(), false); } /* -- 2.43.0