[RFC PATCH 0/2] RISC-V Sspesa: QEMU model support

This QEMU series adds support for the Sspesa (Precise Event
Sample Attribution) extension.

The first patch adds the 'sspesa' CPU property, the ISA string/DT entry,
and the shpmspc/shpmsdata CSRs. It also allows menvcfg.CDE to be set
when Sspesa is enabled, and adds 'ssplcofi' which is implied by Sspesa
so that it is advertised automatically. The second patch captures the
overflowing counter ID in shpmsdata at overflow time and latches shpmspc
with the interrupted instruction address at LCOFI delivery

Note: this series applies on top of the previously posted fix
"target/riscv: Fix LCOFI masking in sie/sip/mvip", which is required for
counter-overflow interrupts to be delivered and cleared correctly.

Reproducing the full setup:

Sspesa support requires three projects: OpenSBI, Linux and QEMU. The
matching branches are:

  OpenSBI: https://github.com/mdchitale/opensbi/tree/riscv_sspesa_rfc_v1
  Linux:   https://github.com/mdchitale/linux/tree/riscv_sspesa_rfc_v1
  QEMU:    https://github.com/mdchitale/qemu/tree/riscv_sspesa_rfc_v1

To test Sspesa, build OpenSBI, Linux and QEMU from the branches above,
then boot Linux with:

  qemu-system-riscv64 -nographic -machine virt -smp 2 -m 2G \
    -cpu rv64,sscofpmf=on,sspesa=on \
    -bios /path/to/fw_dynamic.bin -kernel /path/to/Image \
    -drive file=/path/to/rootfs.img,id=hd0,format=raw,if=none \
    -device virtio-blk-device,drive=hd0 \
    -append "root=/dev/vda rw console=ttyS0 earlycon=sbi"

With all three in place, a counter overflow (e.g. 'perf record -e
cycles -c 1000000 -- <workload>') is attributed using the
hardware-provided sample PC (shpmspc) and counter ID (shpmsdata)
instead of falling back to epc.

Mayuresh Chitale (2):
  target/riscv: Add Sspesa extension and sample CSRs
  target/riscv: Capture Sspesa sample PC and counter ID on overflow

 target/riscv/cpu.c                | 13 ++++-
 target/riscv/cpu.h                |  6 +++
 target/riscv/cpu_bits.h           |  7 +++
 target/riscv/cpu_cfg_fields.h.inc |  2 +
 target/riscv/tcg/cpu_helper.c     |  6 +++
 target/riscv/tcg/csr.c            | 84 ++++++++++++++++++++++++++++++-
 target/riscv/tcg/pmu.c            | 27 ++++++++++
 7 files changed, 142 insertions(+), 3 deletions(-)

-- 
2.43.0