Re: [PATCH 3/5] target/riscv/tcg/debug: adjust 'timing' bit for Debug 1.0

On Wed, 2026-08-05 at 15:25 -0300, Daniel Henrique Barboza wrote:
> Version 1.0 changed the 'timing' bit.  It is now bit 18.
> 
> Signed-off-by: Daniel Henrique Barboza
> <[email protected]>

Reviewed-by: Alistair Francis <[email protected]>

Alistair

> ---
>  target/riscv/tcg/debug.c | 7 ++++++-
>  target/riscv/tcg/debug.h | 3 ++-
>  2 files changed, 8 insertions(+), 2 deletions(-)
> 
> diff --git a/target/riscv/tcg/debug.c b/target/riscv/tcg/debug.c
> index 2191928761..8b23c8d045 100644
> --- a/target/riscv/tcg/debug.c
> +++ b/target/riscv/tcg/debug.c
> @@ -584,10 +584,15 @@ static target_ulong
> type6_mcontrol6_validate(CPURISCVState *env,
>      warn_always_zero_bit(ctrl, TYPE6_MATCH, "match");
>      warn_always_zero_bit(ctrl, TYPE6_CHAIN, "chain");
>      warn_always_zero_bit(ctrl, TYPE6_ACTION, "action");
> -    warn_always_zero_bit(ctrl, TYPE6_TIMING, "timing");
>      warn_always_zero_bit(ctrl, TYPE6_SELECT, "select");
>      warn_always_zero_bit(ctrl, TYPE6_HIT, "hit");
>  
> +    if (debug_trigger_version_1_0(env)) {
> +        warn_always_zero_bit(ctrl, TYPE6_TIMING, "timing");
> +    } else {
> +        warn_always_zero_bit(ctrl, TYPE6_TIMING_0_13, "timing");
> +    }
> +
>      /* validate size encoding */
>      size = extract32(ctrl, 16, 4);
>      if (access_size[size] == -1) {
> diff --git a/target/riscv/tcg/debug.h b/target/riscv/tcg/debug.h
> index a25d099b37..eb635bc277 100644
> --- a/target/riscv/tcg/debug.h
> +++ b/target/riscv/tcg/debug.h
> @@ -98,7 +98,8 @@ typedef enum {
>  #define TYPE6_CHAIN     BIT(11)
>  #define TYPE6_ACTION    (0xf << 12)
>  #define TYPE6_SIZE      (0xf << 16)
> -#define TYPE6_TIMING    BIT(20)
> +#define TYPE6_TIMING       BIT(18)
> +#define TYPE6_TIMING_0_13  BIT(20)
>  #define TYPE6_SELECT    BIT(21)
>  #define TYPE6_HIT       BIT(22)
>  #define TYPE6_VU        BIT(23)