Re: [PATCH v2 1/3] disas/riscv.c: Correct indent for checkpatch

On Thu, 2026-07-16 at 15:24 -0300, Daniel Henrique Barboza wrote:
> 
> 
> On 7/16/2026 12:46 PM, [email protected] wrote:
> > From: Frédéric Pétrot <[email protected]>
> > 
> > Trival indentation patch on the cbo/lq relevant code, in
> > preparation
> 
> s/Trival/Trivial
> 
> 
> > for modifications in that part.
> > 
> 
> 
> Fixes: 9273cda722 ("disas/riscv.c: add 'cbo' insns to disassembler")
> 
> > Signed-off-by: Frédéric Pétrot
> > <[email protected]>
> > ---
> 
> Reviewed-by: Daniel Henrique Barboza
> <[email protected]>
> 
> 
> 
> If no more changes are need I believe the maintainer can fixup the
> typo before
> queuing. No need to send a v3 because of it.

Sorry I missed this. Do you mind rebasing this on the latest master and
sending a v3?

Alistair

> 
> 
> Cheers,
> Daniel
> 
> 
> 
> 
> >   disas/riscv.c | 38 +++++++++++++++++++-------------------
> >   1 file changed, 19 insertions(+), 19 deletions(-)
> > 
> > diff --git a/disas/riscv.c b/disas/riscv.c
> > index 7f1b262773..689502f083 100644
> > --- a/disas/riscv.c
> > +++ b/disas/riscv.c
> > @@ -2887,25 +2887,25 @@ static void decode_inst_opcode(rv_decode
> > *dec, rv_isa isa)
> >               case 0: op = rv_op_fence; break;
> >               case 1: op = rv_op_fence_i; break;
> >               case 2:
> > -               /*
> > -                * 'lq' shares the "(...) 010 ..... 0001111" opcode
> > space
> > -                * with 'cbo' insns.  Check the next 5 bits to
> > select
> > -                * what we want:
> > -                *
> > -                * cbo_inval  0000000 00000 ..... 010 00000 0001111
> > -                * cbo_clean  0000000 00001 ..... 010 00000 0001111
> > -                * cbo_flush  0000000 00010 ..... 010 00000 0001111
> > -                * cbo_zero   0000000 00100 ..... 010 00000 0001111
> > -                *
> > -                * Anything that doesn't match these will default
> > to 'lq'.
> > -                */
> > -               switch ((inst >> 17) & 0b11111) {
> > -               case 0: op = rv_op_cbo_inval; break;
> > -               case 1: op = rv_op_cbo_clean; break;
> > -               case 2: op = rv_op_cbo_flush; break;
> > -               case 4: op = rv_op_cbo_zero; break;
> > -               default: op = rv_op_lq; break;
> > -               }
> > +                /*
> > +                 * 'lq' shares the "(...) 010 ..... 0001111"
> > opcode space
> > +                 * with 'cbo' insns.  Check the next 5 bits to
> > select
> > +                 * what we want:
> > +                 *
> > +                 * cbo_inval  0000000 00000 ..... 010 00000
> > 0001111
> > +                 * cbo_clean  0000000 00001 ..... 010 00000
> > 0001111
> > +                 * cbo_flush  0000000 00010 ..... 010 00000
> > 0001111
> > +                 * cbo_zero   0000000 00100 ..... 010 00000
> > 0001111
> > +                 *
> > +                 * Anything that doesn't match these will default
> > to 'lq'.
> > +                 */
> > +                switch ((inst >> 17) & 0b11111) {
> > +                case 0: op = rv_op_cbo_inval; break;
> > +                case 1: op = rv_op_cbo_clean; break;
> > +                case 2: op = rv_op_cbo_flush; break;
> > +                case 4: op = rv_op_cbo_zero; break;
> > +                default: op = rv_op_lq; break;
> > +                }
> >               }
> >               break;
> >           case 4:
>