[PATCH 12/13] hw/riscv/trace-encoder.c: remaining fields to ram-sink as RO values

 - set trRamActive RO = 1 (always active)
 - set trRamEnable RO = 1 (always enabled)
 - set trRamMode RO = 1 (only SMEM mode)
 - set trRamStopOnWrap RO = 0 (not supported)
 - set trRamMemFormat RO = 0 (memory formatted as plain bytes)
 - set trRamAsyncFreq RO = 0 (alignment synchronization packets disabled)
 - set trRamHasSMEM = 1 (RAM sink supports SMEM)

Signed-off-by: Konstantin Semichastnov <[email protected]>
---
 hw/riscv/trace-ram-sink.c | 22 +++++++++++++++++++++-
 hw/riscv/trace-ram-sink.h |  1 +
 2 files changed, 22 insertions(+), 1 deletion(-)

diff --git a/hw/riscv/trace-ram-sink.c b/hw/riscv/trace-ram-sink.c
index c273335fec..03ffa9caae 100644
--- a/hw/riscv/trace-ram-sink.c
+++ b/hw/riscv/trace-ram-sink.c
@@ -40,13 +40,33 @@
                                R_TR_RAM_IMPL_HAS_SRAM_MASK | \
                                R_TR_RAM_IMPL_HAS_SMEM_MASK)
 
-#define R_TR_RAM_IMPL_RESET (BIT(0) | 0x9 << 8)
+#define R_TR_RAM_IMPL_RESET (BIT(0) | 0x9 << 8 | R_TR_RAM_IMPL_HAS_SMEM_MASK)
+
+static uint64_t tr_ramsink_ctrl_set_hardwire_vals(uint64_t input)
+{
+    input = FIELD_DP32(input, TR_RAM_CONTROL, ACTIVE, 1);
+    input = FIELD_DP32(input, TR_RAM_CONTROL, ENABLE, 1);
+    input = FIELD_DP32(input, TR_RAM_CONTROL, MODE, 1);
+    input = FIELD_DP32(input, TR_RAM_CONTROL, STOP_ON_WRAP, 0);
+    input = FIELD_DP32(input, TR_RAM_CONTROL, MEM_FORMAT, 0);
+    input = FIELD_DP32(input, TR_RAM_CONTROL, ASYNC_FREQ, 0);
+
+    return input;
+}
+
+static uint64_t tr_ramsink_ctrl_prew(RegisterInfo *reg, uint64_t val)
+{
+    val = tr_ramsink_ctrl_set_hardwire_vals(val);
+
+    return val;
+}
 
 static RegisterAccessInfo tr_ramsink_regs_info[] = {
     {   .name = "TR_RAM_CONTROL", .addr = A_TR_RAM_CONTROL,
         .rsvd = R_TR_RAM_CONTROL_RSVP_BITS,
         .reset = R_TR_RAM_CONTROL_RESET,
         .ro = R_TR_RAM_CONTROL_RO_BITS,
+        .pre_write = tr_ramsink_ctrl_prew,
     },
     {   .name = "TR_RAM_IMPL", .addr = A_TR_RAM_IMPL,
         .rsvd = R_TR_RAM_IMPL_RSVP_BITS,
diff --git a/hw/riscv/trace-ram-sink.h b/hw/riscv/trace-ram-sink.h
index 0a7225642c..e516b73e00 100644
--- a/hw/riscv/trace-ram-sink.h
+++ b/hw/riscv/trace-ram-sink.h
@@ -28,6 +28,7 @@ REG32(TR_RAM_CONTROL, 0x0)
     FIELD(TR_RAM_CONTROL, MODE, 4, 1)
     FIELD(TR_RAM_CONTROL, STOP_ON_WRAP, 8, 1)
     FIELD(TR_RAM_CONTROL, MEM_FORMAT, 9, 2)
+    FIELD(TR_RAM_CONTROL, ASYNC_FREQ, 12, 3)
     /* reserved bits */
     FIELD(TR_RAM_CONTROL, RSVP1, 2, 1)
     FIELD(TR_RAM_CONTROL, RSVP2, 5, 3)

-- 
2.43.0