[PATCH 10/13] test/qtest/riscv-trace-test: add test-ntrace-simple qtest

Add a simple smoke test for the ntrace encoder/trace ram sink integration
with the RISC-V 'virt' machine.

Signed-off-by: Konstantin Semichastnov <[email protected]>
---
 tests/qtest/riscv-trace-test.c | 59 +++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 58 insertions(+), 1 deletion(-)

diff --git a/tests/qtest/riscv-trace-test.c b/tests/qtest/riscv-trace-test.c
index fe1cc85358..66069f7a56 100644
--- a/tests/qtest/riscv-trace-test.c
+++ b/tests/qtest/riscv-trace-test.c
@@ -21,6 +21,7 @@ REG32(TR_TE_CONTROL, 0x0)
     FIELD(TR_TE_CONTROL, ACTIVE, 0, 1)
     FIELD(TR_TE_CONTROL, ENABLE, 1, 1)
     FIELD(TR_TE_CONTROL, INST_TRACING, 2, 1)
+    FIELD(TR_TE_CONTROL, FORMAT, 24, 3)
 
 REG32(TR_RAM_START_LOW, 0x010)
     FIELD(TR_RAM_START_LOW, ADDR, 0, 32)
@@ -99,7 +100,61 @@ static void test_trace_simple(void)
     g_assert(1 == FIELD_EX32(reg, TR_TE_CONTROL, INST_TRACING));
 
     g_test_timer_start();
-    for (;;) {
+    while (true) {
+        reg_tram_writep = test_read_tram_writep(qts);
+        if (reg_tram_writep > reg_tram_start) {
+            break;
+        }
+
+        g_assert(g_test_timer_elapsed() <= timeout_sec);
+    }
+
+    qtest_quit(qts);
+}
+
+static void test_ntrace_simple(void)
+{
+    QTestState *qts = qtest_init("-machine virt -accel tcg -d in_asm");
+    double timeout_sec = 0.5;
+    uint64_t reg_tram_start, reg_tram_writep;
+    uint32_t reg;
+
+    /* trTeActive := 1 */
+    reg = test_read_te_control(qts);
+    reg = FIELD_DP32(reg, TR_TE_CONTROL, ACTIVE, 1);
+    test_write_te_control(qts, reg);
+    reg = test_read_te_control(qts);
+    g_assert(1 == FIELD_EX32(reg, TR_TE_CONTROL, ACTIVE));
+
+    /* trTeEnable := 1 */
+    reg = FIELD_DP32(reg, TR_TE_CONTROL, ENABLE, 1);
+    test_write_te_control(qts, reg);
+    reg = test_read_te_control(qts);
+    g_assert(1 == FIELD_EX32(reg, TR_TE_CONTROL, ENABLE));
+
+    /* trTeFormat := 1 (ntrace) */
+    reg = FIELD_DP32(reg, TR_TE_CONTROL, FORMAT, 1);
+    test_write_te_control(qts, reg);
+    reg = test_read_te_control(qts);
+    g_assert(1 == FIELD_EX32(reg, TR_TE_CONTROL, FORMAT));
+
+    /*
+     * Verify if RAM Sink write pointer is equal to
+     * ramstart before start tracing.
+     */
+    reg_tram_start = test_read_tram_ramstart(qts);
+    g_assert(reg_tram_start > 0);
+    reg_tram_writep = test_read_tram_writep(qts);
+    g_assert(reg_tram_writep == reg_tram_start);
+
+    /* trTeInstTracing := 1 */
+    reg = FIELD_DP32(reg, TR_TE_CONTROL, INST_TRACING, 1);
+    test_write_te_control(qts, reg);
+    reg = test_read_te_control(qts);
+    g_assert(1 == FIELD_EX32(reg, TR_TE_CONTROL, INST_TRACING));
+
+    g_test_timer_start();
+    while (true) {
         reg_tram_writep = test_read_tram_writep(qts);
         if (reg_tram_writep > reg_tram_start) {
             break;
@@ -116,5 +171,7 @@ int main(int argc, char *argv[])
     g_test_init(&argc, &argv, NULL);
     qtest_add_func("/riscv-trace-test/test-trace-simple",
                    test_trace_simple);
+    qtest_add_func("/riscv-trace-test/test-ntrace-simple",
+                   test_ntrace_simple);
     return g_test_run();
 }

-- 
2.43.0