Re: [PATCH v3 0/1] target/riscv: correct cbo and lq disassembly

On Tue, 2026-08-25 at 12:09 +0200,
[email protected] wrote:
> From: Frédéric Pétrot <[email protected]>
> 
> The CBO instructions were, AFAIU, disassembled erroneously.
> In addition, lq (load-quad, a RV128 instruction) shares the same
> opcode space as the CBOs, which also led to incorrect dasm for that
> instruction (understandable since RV128 is an experimental feature).
> To avoid overlaps, we now require that lq is decoded only if
> rd is not 0, as CBO requires the field corresponding to rd to be
> zero,
> both in dasm and decodetree.
> 
> Changes in v3:
> - rebase on master
> - squash the 3 original patches, at they did not make sense
>   anymore after rebasing
> 
> Frédéric Pétrot (1):
>   disas/riscv.c: Correct dasm for cbo and lq

Thanks!

Applied to riscv-to-apply.next

Alistair

> 
>  disas/riscv.c | 18 ++++++++++--------
>  1 file changed, 10 insertions(+), 8 deletions(-)