Re: [PATCH 0/2] Fixup TCG for SH-4 FPU instructions fipr and ftrv

On 30.06.2026 00:49, Randy Schifflin wrote:
> SH-4 manual for reference:
> https://0x04.net/~mwk/doc/sh/e602156_sh4.pdf
> 
> There are two issues with the current TCG code generation
> for the `fipr` and `ftrv` instructions. Firstly, they incorrectly
> check that the PR flag of the FPSCR register is high. The manual
> states these instructions are only defined when that flag is 0.
> Secondly, they take as operands a vector index 0-3, but treat
> them as offsets into the floating point register list. Vectors
> span four floating point registers, and thus each index needs to be
> multiplied by 4 to translate to the correct register offset.
> 
> This PR adds simple TCG tests for the `fipr` and `ftrv` instructions,
> and fixes the issues above by ensuring the PR flag of FPSCR is 0 and
> properly translating the vector index operand to its register offset.
> 
> Signed-off-by: Randy Schifflin <[email protected]>
> ---
> Randy Schifflin (2):
>        target/sh4: add tests for sh4 fipr and ftrv instructions
>        target/sh4: fixup tcg for sh4 fipr/ftrv instructions
> 
>   target/sh4/op_helper.c        |  2 +-
>   target/sh4/translate.c        | 15 +++----
>   tests/tcg/sh4/Makefile.target |  7 +++
>   tests/tcg/sh4/test-fpu-fipr.c | 64 ++++++++++++++++++++++++++++
>   tests/tcg/sh4/test-fpu-ftrv.c | 99 +++++++++++++++++++++++++++++++++++++++++++
>   5 files changed, 176 insertions(+), 11 deletions(-)


This looks like qemu-stable material.
I'm picking this up for currently active qemu-stable series.
Please let me know if I should not.

It'd be nice to have the testcase applied to master too (I'll
pick it up for stable series as well, if I wont forget :)

Thanks,

/mjt