[PATCH v2 0/2] Fixup TCG for SH-4 FPU instructions fipr and ftrv

SH-4 manual for reference: 
https://0x04.net/~mwk/doc/sh/e602156_sh4.pdf

There are two issues with the current TCG code generation
for the `fipr` and `ftrv` instructions. Firstly, they incorrectly
check that the PR flag of the FPSCR register is high. The manual
states these instructions are only defined when that flag is 0.
Secondly, they take as operands a vector index 0-3, but treat
them as offsets into the floating point register list. Vectors
span four floating point registers, and thus each index needs to be
multiplied by 4 to translate to the correct register offset.

This PR adds simple TCG tests for the `fipr` and `ftrv` instructions,
and fixes the issues above by ensuring the PR flag of FPSCR is 0 and
properly translating the vector index operand to its register offset.

Signed-off-by: Randy Schifflin <[email protected]>
---
Changes in v2:
- Lint test-fpu-fipr.c and test-fpu-ftrv.c to conform with style guide
- Link to v1: https://lore.kernel.org/qemu-devel/20260629-fixup-sh4-tcg-fpu-instructions-b4-v1-0-4356b305f971@gmail.com

---
Randy Schifflin (2):
      target/sh4: add tests for sh4 fipr and ftrv instructions
      Fixes TCG generation for sh4 `fipr` and `ftrv` instructions.

 tests/tcg/sh4/Makefile.target |   7 +++
 tests/tcg/sh4/test-fpu-fipr.c |  72 ++++++++++++++++++++++++++++
 tests/tcg/sh4/test-fpu-ftrv.c | 108 ++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 187 insertions(+)
---
base-commit: e1705a25aff35635c360bbaba4c2731d019a422a
change-id: 20260629-fixup-sh4-tcg-fpu-instructions-b4-963cdafd33bf

Best regards,
-- 
Randy Schifflin <[email protected]>