Re: [Intel-wired-lan] [PATCH iwl-net v3] ice: fall back to SBQ when LL PHY timer interface times out

> -----Original Message-----
> From: Intel-wired-lan <[email protected]> On Behalf Of Przemyslaw Korba
> Sent: 05 June 2026 17:36
> To: [email protected]
> Cc: [email protected]; Nguyen, Anthony L <[email protected]>; Kitszel, Przemyslaw <[email protected]>; Ilichev, Konstantin <[email protected]>; Lobakin, Aleksander <[email protected]>; Korba, Przemyslaw <[email protected]>
> Subject: [Intel-wired-lan] [PATCH iwl-net v3] ice: fall back to SBQ when LL PHY timer interface times out
>
> The low-latency (LL) PHY timer interface relies on a tight, atomic poll of the PF_SB_ATQBAL register with a 2ms timeout. After an NVM update / EMPR, FW may need significantly longer than 2ms to start responding to > ATQBAL commands. The first PHY adjust or incval write issued by
> ice_ptp_rebuild_owner() fails with -ETIMEDOUT.
>
>Fix this by falling back to the existing SBQ-based PHY register write path when LL times out. This makes sure PTP is initialized when FW takes longer than expected to come back online.
>
> Steps to reproduce:
> ./nvmupdate64e -if devlink -f
> Update E810 card with nvmupdate64e, and observe dmesg errors:
>   Failed to write PHC increment value, status -110
>   PTP reset failed, error: -110 (-ETIMEDOUT)
>

Tested-by: Rinitha S <[email protected]> (A Contingent worker at Intel)